Effect of glitches against masked AES S-box implementation and countermeasure

IET Information Security

Volumn 3, Issue 1, 2009, Pages 34-44

  Alam, M ^a   Ghosh, S ^a   Mohan, M J ^a   Mukhopadhyay, D ^a   Chowdhury, D R ^a   Gupta, I S ^a  

^a INDIAN INSTITUTE OF TECHNOLOGY   (India)

Author keywords

[No Author keywords available]

Indexed keywords

CRYPTOGRAPHY; LOGIC CIRCUITS; SWITCHING CIRCUITS;

AES ALGORITHMS; AMOUNT OF INFORMATIONS; CMOS CIRCUITS; COMBINATIONAL PATHS; CRYPTOGRAPHIC ALGORITHMS; DIFFERENTIAL POWER ANALYSIS; DPA ATTACKS; INPUT VECTORS; POWER ATTACKS; SIDE-CHANNEL INFORMATIONS;

TIMING CIRCUITS;

EID: 60749098239     PISSN: 17518709     EISSN: 17518717     Source Type: Journal    
DOI: 10.1049/iet-ifs:20080041     Document Type: Article

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