Rijndael FPGA implementation utilizing look-up tables

IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation

Volumn , Issue , 2001, Pages 349-360

  McLoone, M ^a   McCanny, J V ^a  

^a QUEEN'S UNIVERSITY BELFAST   (United Kingdom)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; FIELD PROGRAMMABLE GATE ARRAYS; FUNCTIONS; POLYNOMIALS; RESPONSE TIME (COMPUTER SYSTEMS); TABLE LOOKUP;

ENCRYPTION ALGORITHMS; RIJNDAEL ROUND FUNCTION;

CRYPTOGRAPHY;

EID: 0035150340     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (10)

1. The Rijndael block cipher: AES proposal
2. Apparatus for selectably encrypting and decrypting data
3. High performance single-chip FPGA Rijndael algorithm implementations
4. Comparison of the hardware performance of the AES candidates using reconfigurable hardware
5. A comparative study of performance of AES candidates using FPGAs
6. An FPGA implementation and performance evaluation of the AES block cipher candidate algorithm finalists