Sub-threshold operation of a timing error detection latch

2009 Ph.D. Research in Microelectronics and Electronics, PRIME 2009

Volumn , Issue , 2009, Pages 124-127

  Turnquist, Matthew J ^a   Koskinen, Lauri ^a  

^a AALTO UNIVERSITY   (Finland)

Author keywords

[No Author keywords available]

Indexed keywords

ACTIVITY FACTOR; AVERAGE POWER; CLOCK PERIOD; DIGITAL CMOS; EXPONENTIAL DEPENDENCE; LOW POWER APPLICATION; MINIMUM ENERGY; MINIMUM ENERGY POINT; OPERATING VOLTAGE RANGE; SUBTHRESHOLD; SUBTHRESHOLD OPERATION; SUPPLY VOLTAGES; TIMING ERROR DETECTION;

DRAIN CURRENT; INTEGRATED CIRCUIT LAYOUT; MICROELECTRONICS; THRESHOLD ELEMENTS; TIME MEASUREMENT;

ERROR DETECTION;

EID: 70449504155     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/RME.2009.5201304     Document Type: Conference Paper

References (9)

1. S. Henzler, Power Management of Digital Circuits in Deep Sub-Micron CMOS Technologies. Springer, 2007.
2. M. Elgebaly and M. Sachdev, "Variation-aware adaptive voltage scaling system," IEEE Trans. VLSI Syst., vol.15, no.5, pp. 560-571, 2007.
3. S. Akui, K. Seno, M. Nakai, T. Meguro, T. Seki, T. Kondo, A. Hashiguchi, H. Kawahara, K. Kumano, and M. Shimura, M. A10 Shimura, "Dynamic voltage and frequency management for a low-power embedded microprocessor," in Proc. Digest of Technical Papers Solid-State Circuits Conference ISSCC. 2004 IEEE International, K. Seno, Ed., 2004, pp. 64-513 Vol.1.
4. A. Wang, B. Calhoun, and A. Chandrakasan, Sub-Threshold Design for Ultra Low-Power Systems. Springer, 2005.
5. L. Anghel and M. Nicolaidis, "Cost reduction and evaluation of a temporary faults detecting technique," in Proc. Design Automation and Test in Europe Conference and Exhibition 2000, 2000, pp. 591-598.
6. D. Blaauw, "Razor ii: In situ error detection and correction for pvt and ser tolerance," ISSCC 2008, 2008.
7. T. Austin, D. Blaauw, T. Mudge, and K. Flautner, "Making typical silicon matter with razor," IEEE Computer Society, vol.37, no.3, pp. 57-65, 2004.
8. K. A. Bowman, J. W. Tschanz, N. S. Kim, J. C. Lee, C. B. Wilkerson, S.-L. L. Lu, T. Karnik, and V. K. De, "Energy-efficient and metastabilityimmune timing-error detection and instruction-replay-based recovery circuits for dynamic-variation tolerance," in Proc. Digest of Technical Papers. IEEE International Solid-State Circuits Conference ISSCC 2008, 2008, pp. 402-623.
9. S. Das, C. Tokunaga, S. Pant, W. H. Ma, S. Kalaiselvan, K. Lai, D. M. Bull, and D. T. Blaauw, "Razorii: In situ error detection and correction for pvt and ser tolerance," IEEE J. Solid-State Circuits, vol.44, no.1, pp. 32-48, 2009.