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Volumn , Issue , 2009, Pages 315-322
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Performance-effective compaction of standard-cell libraries for digital design
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Author keywords
Algorithm; Complexity reduction; Digital design; Standard cell library
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Indexed keywords
ALGORITHM COMPLEXITY;
BENCHMARK CIRCUIT;
CIRCUIT DESIGNS;
CIRCUIT SYNTHESIS;
DIGITAL DESIGNS;
HIGH-SPEED CIRCUITRY;
LOW-POWER CONSUMPTION;
OPTIMIZATION CRITERIA;
REDUCTION STRATEGY;
SMALL AREA;
STANDARD-CELL;
SYNTHESIS PROCESS;
SYNTHESIS TIME;
SYNTHESIS TOOL;
TECHNOLOGY NODES;
CELLS;
COMPACTION;
DESIGN;
INTEGRATED CIRCUIT MANUFACTURE;
LIBRARIES;
MAINTENANCE;
OPTIMIZATION;
STANDARDS;
DIGITAL LIBRARIES;
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EID: 74549123645
PISSN: None
EISSN: None
Source Type: Conference Proceeding
DOI: 10.1109/DSD.2009.139 Document Type: Conference Paper |
Times cited : (7)
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References (8)
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