A 240mV 1MHz, 340mV 10MHz, 40nm CMOS, 252 bits frame decoder using ultra-low voltage circuit design platform

2011 18th IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2011

Volumn , Issue , 2011, Pages 105-108

  Clerc, Sylvain ^a   Abouzeid, Fady ^a   Argoud, Fabrice ^a   Kumar, Abhay ^b   Kumar, Rajesh ^b   Roche, Philippe ^a  

^a STMICROELECTRONICS   (France)

^b STMICROELECTRONICS   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; FLIP FLOP CIRCUITS; INTEGRATED CIRCUIT DESIGN; INTEGRATED CIRCUIT MANUFACTURE; TIMING CIRCUITS;

CAD SIMULATIONS; CIRCUIT IMPLEMENTATION; CRITICAL PATHS; FORWARD BODY BIASING; TEMPERATURE RANGE; ULTRA LOW VOLTAGE DESIGNS (ULV); ULTRA-LOW-VOLTAGE; VOLTAGE RANGES;

COMPUTER AIDED DESIGN;

EID: 84863075946     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICECS.2011.6122228     Document Type: Conference Paper

References (12)

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