A 31ns random cycle VCAT-based 4F2 DRAM with enhanced cell efficiency

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue , 2009, Pages 132-133

  Song, Ki Whan ^a   Kim, Jin Young ^a   Kim, Huijung ^b   Chung, Hyun Woo ^b   Kim, Hyungi ^b   Kim, Kanguk ^b   Park, Hwan Wook ^a   Kang, Hyun Chul ^a   Kim, Sua ^a   Tak, Nam Kyun ^a   Park, Dukha ^a   Kim, Woo Seop ^a   Lee, Yeong Taek ^a   Oh, Yong Chul ^b   Jin, Gyo Young ^b   Yoo, Jeihwan ^a   Oh, Kyungseok ^b   Kim, Changhyun ^a   Lee, Won Seong ^a  

^a SAMSUNG Electronics   (South Korea)

^b ATD and ATD ^*

Author keywords

4F2; DRAM and VCAT

Indexed keywords

4F2; ARRAY SIZES; CELL ARRAY; CELL EFFICIENCY; CORE DESIGN; DESIGN RULES; DRAM AND VCAT; RANDOM CYCLE; SMALL AREA; TEST CHIPS;

VLSI CIRCUITS;

DYNAMIC RANDOM ACCESS STORAGE;

EID: 70449367473     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (9)

1. K. Kim et al., IEDM Tech. Dig., pp. 27-30, 2007.
2. Y. Park et al., IEDM Tech. Dig., pp. 391-394, 2001.
3. D.H. Kim et al., IEDM Tech. Dig., pp. 69-72, 2004.
4. S. Maeda et al., VLSI Tech. Dig., pp. 133-134, 2004.
5. F. Hofmann et al., ESSDERC Dig., pp.131-134, 2001.
6. J.-M. Yoon et al., DRC Tech. Dig., pp 259-260, 2006.
7. S. Watanabe et al., IEEE J. Solid-State Cir., pp. 960-971, 1995.
8. J. Beintner et al., VLSI Tech Dig., pp. 243-246, 2003.
9. J. Beintner et al., IEEE Elec. Dev. Lett., pp. 259-261, 2004.