-
1
-
-
26444487906
-
"Charge pumping SOS-MOS transistor memory"
-
Washington, DC
-
N. Sasaki, M. Nakano, T. Iwai, and R. Togei, "Charge pumping SOS-MOS transistor memory," in IEDM Tech. Dig., Washington, DC, 1978, pp. 356-359.
-
(1978)
IEDM Tech. Dig.
, pp. 356-359
-
-
Sasaki, N.1
Nakano, M.2
Iwai, T.3
Togei, R.4
-
2
-
-
0025433827
-
"The multistable charge-controlled memory effect in SOI MOS transistors at low temperatures"
-
May
-
M. R. Tack, M. Gao, C. L. Claeys, and G. J. Declerck, "The multistable charge-controlled memory effect in SOI MOS transistors at low temperatures," IEEE Trans. Electron Devices, vol. 37, no. 5, pp. 1373-1382, May 1990.
-
(1990)
IEEE Trans. Electron Devices
, vol.37
, Issue.5
, pp. 1373-1382
-
-
Tack, M.R.1
Gao, M.2
Claeys, C.L.3
Declerck, G.J.4
-
3
-
-
0027889264
-
"A capacitorless DRAM cell on SOI substrate"
-
Washington, DC
-
H. Wann and C. Hu, "A capacitorless DRAM cell on SOI substrate," in IEDM Tech. Dig., Washington, DC, 1993, pp. 635-638.
-
(1993)
IEDM Tech. Dig.
, pp. 635-638
-
-
Wann, H.1
Hu, C.2
-
4
-
-
0035167288
-
"A capacitor-less SOI 1T-DRAM concept"
-
Durango, CO
-
S. Okhonin, M. Nagoga, J. M. Sallese, and P. Fazan, "A capacitor-less SOI 1T-DRAM concept," in Proc. Int. SOI Conf., Durango, CO, 2001, pp. 153-154.
-
(2001)
Proc. Int. SOI Conf.
, pp. 153-154
-
-
Okhonin, S.1
Nagoga, M.2
Sallese, J.M.3
Fazan, P.4
-
5
-
-
0141649575
-
"FBC (floating body cell) for embedded DRAM on SOI"
-
Kyoto, Japan
-
K. Inoh, T. Shino, H. Yamada, H. Nakajima, Y. Minami, T. Yamada, T. Ohsawa, T. Higashi, K. Fujita, T. Ikehashi, T. Kajiyama, Y. Fukuzumi, T. Hamamoto, and H. Ishiuchi, "FBC (floating body cell) for embedded DRAM on SOI," in Symp. VLSI Tech. Dig., Kyoto, Japan, 2003, pp. 63-64.
-
(2003)
Symp. VLSI Tech. Dig.
, pp. 63-64
-
-
Inoh, K.1
Shino, T.2
Yamada, H.3
Nakajima, H.4
Minami, Y.5
Yamada, T.6
Ohsawa, T.7
Higashi, T.8
Fujita, K.9
Ikehashi, T.10
Kajiyama, T.11
Fukuzumi, T.12
Hamamoto, T.13
Ishiuchi, H.14
-
6
-
-
4544260160
-
"Highly scalable FBC (floating body cell) with 25 nm BOX structure for embedded DRAM applications"
-
Honolulu, HI
-
T. Shino, T. Higashi, K. Fujita, T. Ohsawa, Y. Minami, T. Yamada, M. Morikado, H. Nakajima, K. Inoh, T. Hamamoto, and A. Nitayama, "Highly scalable FBC (floating body cell) with 25 nm BOX structure for embedded DRAM applications," in Symp. VLSI Tech. Dig., Honolulu, HI, 2004, pp. 132-133.
-
(2004)
Symp. VLSI Tech. Dig.
, pp. 132-133
-
-
Shino, T.1
Higashi, T.2
Fujita, K.3
Ohsawa, T.4
Minami, Y.5
Yamada, T.6
Morikado, M.7
Nakajima, H.8
Inoh, K.9
Hamamoto, T.10
Nitayama, A.11
-
7
-
-
0036456858
-
"Capacitor-less 1-transistor DRAM"
-
Williamsburg, VA
-
P. Fazan, S. Okhonin, M. Nagoga, J. M. Sallese, L. Portmann, R. Ferrant, M. Kayal, M. Pastre, M. Blagojevic, A. Borschberg, and M. Declercq, "Capacitor-less 1-transistor DRAM," in Proc. Int. SOI Conf., Williamsburg, VA, 2002, pp. 10-13.
-
(2002)
Proc. Int. SOI Conf.
, pp. 10-13
-
-
Fazan, P.1
Okhonin, S.2
Nagoga, M.3
Sallese, J.M.4
Portmann, L.5
Ferrant, R.6
Kayal, M.7
Pastre, M.8
Blagojevic, M.9
Borschberg, A.10
Declercq, M.11
-
8
-
-
33645735222
-
"SOI floating body memories for embedded memory applications"
-
Tokyo, Japan
-
P. Fazan, S. Okhonin, and M. Nagoga, "SOI floating body memories for embedded memory applications," in Proc. Ext. Abs. Solid State Devices Mater. (SSDM), Tokyo, Japan, 2004, pp. 228-229.
-
(2004)
Proc. Ext. Abs. Solid State Devices Mater. (SSDM)
, pp. 228-229
-
-
Fazan, P.1
Okhonin, S.2
Nagoga, M.3
-
9
-
-
0842266492
-
"A design of a capacitorless 1T-DRAM cell using gate-induced drain leakage (GIDL) current for low-power and high-speed embedded memory"
-
Washington, DC
-
E. Yoshida and T. Tanaka, "A design of a capacitorless 1T-DRAM cell using gate-induced drain leakage (GIDL) current for low-power and high-speed embedded memory," in IEDM Tech. Dig., Washington, DC, 2003, pp. 913-916.
-
(2003)
IEDM Tech. Dig.
, pp. 913-916
-
-
Yoshida, E.1
Tanaka, T.2
-
10
-
-
0036857083
-
"Memory design using a one-transistor gain cell on SOI"
-
Nov
-
T. Ohsawa, K. Fujita, T. Higashi, Y. Iwata, T. Kajiyama, Y. Asao, and K. Sunouchi, "Memory design using a one-transistor gain cell on SOI," IEEE J. Solid-State Circuits, vol. 37, no. 11, pp. 1510-1522, Nov. 2002.
-
(2002)
IEEE J. Solid-State Circuits
, vol.37
, Issue.11
, pp. 1510-1522
-
-
Ohsawa, T.1
Fujita, K.2
Higashi, T.3
Iwata, Y.4
Kajiyama, T.5
Asao, Y.6
Sunouchi, K.7
-
11
-
-
0026954430
-
"The enhancement of gate-induced-drain leakage (GIDL) current in short-channel SOI MOSFET and its application in measuring lateral bipolar current gain"
-
Nov
-
J. Chen, F. Assaderaghi, P.-K. Ko, and C. Hu, "The enhancement of gate-induced-drain leakage (GIDL) current in short-channel SOI MOSFET and its application in measuring lateral bipolar current gain," IEEE Electron Device Lett., vol. 13, no. 11, pp. 572-574, Nov. 1992
-
(1992)
IEEE Electron Device Lett.
, vol.13
, Issue.11
, pp. 572-574
-
-
Chen, J.1
Assaderaghi, F.2
Ko, P.-K.3
Hu, C.4
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