Scaling of the SOI Field Effect Diode (FED) for memory application

2009 International Semiconductor Device Research Symposium, ISDRS '09

Volumn , Issue , 2009, Pages

  Yang, Y ^a   Gangopadhyay, Aveek ^a   Li, Qiliang ^a   Ioannou, Dimitris E ^a  

^a Krasnow Institute for Advanced Study   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 77949353305     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISDRS.2009.5378045     Document Type: Conference Paper

References (3)

1. 2 T-RAM in a 130 nm SOI CMOS for High-Density High-Performance SRAMS," Proc. IEEE-IEDM, 2004, pp.273-276.
2. H.-J. Cho, F. Nemati et al, "A novel capacitor-less DRAM cell using Thin Capacitively-Coupled Thyristor (TCCT)," Proc. IEEE-IEDM, 2005, pp.321-324.
3. A.A. Salman, S.G. Beebe, M. Emam, M.M. Pelella and D.E. Ioannou, "Field Effect Diode (FED): A novel device for ESD protection in deep sub-micron SOI technologies," Proc. IEEE-IEDM, 2006, pp.109-112.