FPGA implementations of piecewise affine functions based on multi-resolution hyperrectangular partitions

IEEE Transactions on Circuits and Systems I: Regular Papers

Volumn 59, Issue 12, 2012, Pages 2920-2933

  Comaschi, Francesco ^a,b   Genuit, Bart A G ^a   Oliveri, Alberto ^a   Heemels, W P Maurice H ^a   Storace, Marco ^a  

^a EINDHOVEN UNIVERSITY OF TECHNOLOGY   (Netherlands)

^b UNIVERSITY OF GENOA   (Italy)

Author keywords

Digital circuits; digital control; field programmable gate arrays; piecewise linear techniques; predictive control

Indexed keywords

DIGITAL CIRCUITS; DIGITAL CONTROL SYSTEMS; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); LINEAR SYSTEMS; MODEL PREDICTIVE CONTROL; PREDICTIVE CONTROL SYSTEMS;

CONSTRAINED LINEAR SYSTEMS; DIGITAL ARCHITECTURE; DIGITAL CONTROL; ELECTRONIC IMPLEMENTATIONS; EXPLICIT MODEL PREDICTIVE CONTROL; PIECEWISE AFFINE FUNCTIONS; POINT LOCATION PROBLEMS; PREDICTIVE CONTROL;

PIECEWISE LINEAR TECHNIQUES;

EID: 84870507779     PISSN: 15498328     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCSI.2012.2206490     Document Type: Article

References (56)

1. T. Mestl, C. Lemay, and L. Glass, "Chaos in high dimensional neural and gene networks," Physica D, vol. 98, no. 1, pp. 33-52, Nov. 1996. (Pubitemid 126687446)
2. J. Eckmann and E.Moses, "Curvature of co-links uncovers hidden thematic layers in the world-wide web," P. Nat. Acad. Sci. USA, vol. 99, no. 9, pp. 5825-5829, Apr. 2002. (Pubitemid 34493224)
3. W. B. Arthur, "Complexity and the economy," Science, vol. 284, no. 5411, pp. 107-109, Apr. 1999. (Pubitemid 29282057)
4. B. Carreras, V. Lynch, I. Dobson, and D. Newman, "Critical points and transitions in an electric power transmission model for cascading failure blackouts," Chaos, vol. 12, no. 4, pp. 985-994, Dec. 2002. (Pubitemid 36046844)
5. P. Tøndel, T. A. Johansen, and A. Bemporad, "Evaluation of piecewise affine control via binary search tree," Automatica, vol. 39, no. 5, pp. 945-950, 2003.
6. T. A. Johansen, W. Jackson, R. Schreiber, and P. Tøndel, "Hardware synthesis of explicit model predictive controllers," IEEE Trans. Contr. Syst. Technol., vol. 15, no. 1, pp. 191-197, Jan. 2007. (Pubitemid 46056111)
7. R. Rovatti, A. Ferrari, and M. Borgatti, A. Kandel and G. Langholz, Eds., "Automatic implementation of piecewise-linear fuzzy systems addressing memory-performance trade-off," in Fuzzy Hardware: Architectures and Applications. Norwell, MA: Kluwer Academic, 1998, pp. 159-179.
8. P. Echevarria, M. Martínez, J. Echanobe, I. del Campo, and J. Tarela, "Digital hardware implementation of high dimensional fuzzy systems," in Applications of Fuzzy Sets Theory, ser. Lecture Notes in Computer Science. Berlin, Germany: Springer, 2007, pp. 245-252. (Pubitemid 350270285)
9. M. Storace and M. Parodi, "Towards analog implementations of PWL two-dimensional non-linear functions," Int. J. Circuit Theory and Applications, vol. 33, no. 2, pp. 147-160, Mar.-Apr. 2005. (Pubitemid 40416514)
10. M. Storace and T. Poggi, "Digital architectures realizing piecewiselinear multi-variate functions: Two FPGA implementations," Int. J. Circuit Theory and Applications, vol. 39, pp. 1-15, 2011.
11. L. O. Chua, "Section-wise piecewise linear functions. Canonical representation, properties and applications," Proc. IEEE, vol. 65, pp. 915-929, 1977.
12. D. M. W. Leenaerts and W. M. G. van Bokhoven, Piecewise Linear Modelling and Analysis. Boston, MA: Kluwer Academic, 1998.
13. P. Julián, A. Desages, and B. D'Amico, "Orthonormal high level canonical PWL functions with applications to model reduction," IEEE Trans. Circuits Syst. I: Fund. Theory Applicat., vol. 47, no. 5, pp. 702-712, May 2000.
14. M. Storace, P. Julián, and M. Parodi, "Synthesis of nonlinear multiport resistors: A PWL approach," IEEE Trans. Circuits Syst. I: Fund. Theory Applicat., vol. 49, no. 8, pp. 1138-1149, Aug. 2002. (Pubitemid 34974187)
15. P. Julián, "The complete canonical piecewise-linear representation: Functional form for minimal degenerate intersections," IEEE Trans. Circuits Syst. I: Fund. Theory Applicat., vol. 50, no. 3, pp. 387-396, Mar. 2003.
16. C. Wen and X. Ma, "A canonical piecewise-linear representation theorem: Geometrical structures determine representation capability," IEEE Trans. Circuits Syst. II: Expr. Briefs, vol. 58, no. 12, pp. 936-940, Dec. 2011.
17. J. W. Schwartz, "Piecewise linear servomechanisms," Trans. AIEE, vol. 72, pp. 401-405, 1953.
18. E. D. Sontag, "Nonlinear regulation: The piecewise linear approach," IEEE Trans. Automat. Contr., vol. 26, pp. 346-358, 1981.
19. A. Bemporad, F. Borrelli, and M. Morari, "Model predictive control based on linear programming: The explicit solution," IEEE Trans. Automat. Contr., vol. 47, no. 12, pp. 1974-1985, 2002.
20. A. Bemporad, M. Morari, V. Dua, and E. Pistikopoulos, "The explicit linear quadratic regulator for constrained systems," Automatica, vol. 38, no. 1, pp. 3-20, 2002. (Pubitemid 33034535)
21. M. de Berg, M. van Kreveld, M. Overmars, and O. Cheong, Computational Geometry, 3rd ed. Berlin, Germany: Springer-Verlag, 2008.
22. A. Oliveri, A. Oliveri, T. Poggi, and M. Storace, "Circuit implementation of piecewise-affine functions based on a binary search tree," in Proc. 18th Eur. Conf. Circuit Theory and Design (ECCTD'09), Antalya, Turkey, Aug. 23-27, 2009, pp. 145-148.
23. C. Wen, X. Ma, and B. E. Ydstie, "Analytical expression of explicit MPC solution via lattice piecewise-affine function," Automatica, vol. 45, no. 12, pp. 910-917, 2009.
24. F. Bayat, T. A. Johansen, and A. A. Jalali, "Flexible piecewise function evaluation methods based on truncated binary search trees and lattice representation in explicit MPC," IEEE Trans. Contr. Syst. Technol., vol. 20, no. 3, pp. 632-640, May 2012.
25. F. Bayat, T. A. Johansen, and A. A. Jalali, "Using hash tables to manage time-storage complexity in point location problem: Application to explicit MPC," Automatica, vol. 47, pp. 571-577, 2011.
26. M. C. Martinez-Rodriguez, I. Baturone, and P. Brox, "Circuit implementation of piecewise-affine functions based on lattice representation," in Proc. 20th Eur. Conf. Circuit Theory and Design (ECCTD), Linkoping, Sweden, Aug. 29-31, 2011, pp. 644-647.
27. M. C. Martinez-Rodriguez, I. Baturone, and P. Brox, "Design methodology for FPGA implementation of lattice piecewise-affine functions," in Proc. 2011 Int. Conf. Field-Programmable Technology (FPT), Dec. 12-14, 2011, pp. 1-4.
28. A. Bemporad, A. Oliveri, T. Poggi, and M. Storace, "Ultra-fast stabilizing model predictive control via canonical piecewise affine approximations," IEEE Trans. Automat. Contr., vol. 56, pp. 2883-2937, Dec. 2011.
29. S. Summers, C. N. Jones, J. Lygeros, and M. Morari, "A multiresolution approximation method for fast explicit model predictive control," IEEE Trans. Automat. Contr., vol. 56, no. 11, pp. 2530-2541, 2011.
30. T. A. Johansen and A. Grancharova, "Approximate explicit constrained linear model predictive control via orthogonal search tree," IEEE Trans. Automat. Contr., vol. 48, no. 5, pp. 810-815, 2003.
31. B. A. G. Genuit, L. Lu, and W. P. M. H. Heemels, "Approximation of explicit model predictive control using regular piecewise affine functions: An input-to-state stability approach," IET Control Theory and Applications, vol. 6, no. 8, pp. 1015-1028, May 2012.
32. L.Lu,W. P.M. H.Heemels, andA. Bemporad, "Synthesis of low-complexity stabilizing piecewise affine controllers: A control-Lyapunov function approach," in Proc. 50th IEEE Conf. Decision and Control and Eur. Control Conf., Orlando, FL, 2011, pp. 1227-1232.
33. H. Kuhn, "Some combinatorial lemmas in topology," IBM J. Research and Development, vol. 4, pp. 518-524, 1960.
34. M. Parodi, M. Storace, and P. Julián, "Synthesis of multiport resistors with piecewise-linear characteristics: A mixed-signal architecture," Int. J. Circuit Theory and Applications, vol. 33, no. 4, pp. 307-319, Jul.-Aug. 2005. (Pubitemid 41068378)
35. M. Di Federico, T. Poggi, P. Julián, and M. Storace, "Integrated circuit implementation of multi-dimensional piecewise-linear functions," Digital Signal Process., vol. 20, pp. 1723-1732, Dec. 2010.
36. T. Poggi, F. Comaschi, and M. Storace, "Digital circuit realization of piecewise affine functions with non-uniform resolution: Theory and FPGA implementation," IEEE Trans. Circuits Syst. II: Expr. Briefs, vol. 57, no. 2, pp. 131-135, Feb. 2010.
37. M. Floater, E. Quak, andM. Reimers, "Filter bank algorithms for piecewise linear prewavelets on arbitrary triangulations," J. Comput. Appl. Math., vol. 119, pp. 185-207, 2000.
38. E. Suter, "A strategy for the construction of piecewise linear prewavelets over type-1 triangulations in any space dimension," in Mathematical Methods for Curves and Surfaces: Oslo 2000. Nashville, TN: Vanderbilt University, 2001.
39. M. Parodi, M. Gaggero, and M. Storace, "Piecewise linear approximations of multivariate functions: A multiresolution-based compression algorithm suitable for circuit implementation," Appl. Numer. Math., vol. 60, pp. 924-933, 2010.
40. P. Julián, A. Desages, and O. Agamennoni, "High-level canonical piecewise linear representation using a simplicial partition," IEEE Trans. Circuits Syst. I: Fund. Theory Applicat., vol. 46, no. 4, pp. 463-480, Apr. 1999. (Pubitemid 32262741)
41. H. Kuhn, "Simplicial approximation of fixed points," in Proc. Nat. Acad. Sci. USA, 1968, vol. 61, pp. 1238-1242.
42. R. Rovatti, C. Fantuzzi, and S. Simani, "High-speed DSP-based implementation of piecewise-affine and piecewise-quadratic fuzzy systems," Signal Process., vol. 80, pp. 951-963, 2000.
43. E. F. Moore, "Gedanken-experiments on sequential machines," Automata Studies, Annals of Mathematical Studies, vol. 34, pp. 129-153, 1956.
44. G. H. Mealy, "Amethod for synthesizing sequential circuits," Bell Syst. Tech. J., vol. 34, pp. 1045-1079, 1955.
45. M. Storace, L. Repetto, and M. Parodi, "A method for the approximate synthesis of cellular non-linear networks. Part 1: Circuit definition," Int. J. Circuit Theory and Applications, vol. 31, pp. 277-297, 2003.
46. L. Repetto, M. Storace, and M. Parodi, "A method for the approximate synthesis of cellular non-linear networks. Part 2: Circuit reduction," Int. J. Circuit Theory and Applications, vol. 31, pp. 299-313, 2003.
47. M. Chien and E. Kuh, "Solving nonlinear resistive networks using piecewise-linear analysis and simplicial subdivision," IEEE Trans. Circuits Syst., vol. 24, pp. 305-317, 1977. (Pubitemid 8557350)
48. R. Rovatti, M. Borgatti, and R. Guerrieri, "A geometric approach to maximum-speed n-dimensional continuous linear interpolation in rectangular grids," IEEE Trans. Computers, vol. 47, no. 8, pp. 894-899, 1998. (Pubitemid 128738523)
49. V. Pedroni, "Compact hamming-comparator-based rank order filter for digital VLSI and FPGA implementations," in Proc. 2004 IEEE Int. Symp. Circuits and Systems (ISCAS'2004), Vancouver, Canada, May 23-26, 2004, pp. 585-588.
50. D. Q. Mayne and S. Rakovic, "Model predictive control of discrete piecewise affine discrete-time systems," Int. J. Robust and Nonlinear Control, vol. 13, no. 3-4, pp. 261-279, Mar.-Apr. 2003.
51. P. Tøndel, T. A. Johansen, and A. Bemporad, "An algorithm for multiparametric quadratic programming and explicit mpc solutions," Automatica, vol. 39, no. 5, pp. 489-497, 2003.
52. A. Bemporad, Hybrid Toolbox-User's Guide, 2004 [Online]. Available: http://www.dii.unisi.it/hybrid/toolbox
53. T. Poggi, I. Baturone, and M. Storace, "Selection of architectures for PWA functions implementation," Moby-Dic, 7th Framework Programme, Deliverable D4.1, Nov. 2010 [Online]. Available: http://www.mobydic-project.eu/ communication/deliverables
54. F. Borrelli,M. Baotic,A. Bemporad, andM.Morari, "An efficient algorithm for computing the state feedback optimal control law for discrete time hybrid systems," in Proc. 2003 Amer. Control Conf. (ACC'03), Denver, Colorado, Jun. 2003, pp. 4717-4722.
55. M. Kvasnica, P. Grieder, M. Baotic, andM. Morari, "Multi-parametric toolbox (MPT),"Hybrid Systems: Computation and Control, vol. 2993, pp. 121-124, 2004.
56. M. Thompson, "FPGAs accelerate time to market for industrial designs," EE Times 2004 [Online]. Available: http://www.us.design-reuse. com/articles/8190/fpgas-accelerate-time-to-market-for-industrial-designs.html