Constructing virtual architectures on a tiled processor

Proceedings of the CGO 2006 - The 4th International Symposium on Code Generation and Optimization

Volumn , Issue , 2006, Pages 173-184

  Wentzlaff, David ^a   Agarwal, Anant ^a  

^a MASSACHUSETTS INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ACCEPTABLE PERFORMANCE; DYNAMIC INSTRUCTIONS; DYNAMIC RE-CONFIGURATION; DYNAMICALLY RECONFIGURABLE ARCHITECTURE; PARALLEL PROCESSING ELEMENTS; PIPELINE PARALLELISMS; SUPERSCALAR PROCESSOR; VIRTUAL MACHINE CONFIGURATION;

BUILDING MATERIALS; COMPUTER ARCHITECTURE; DYNAMIC MODELS; ENGINES; NETWORK COMPONENTS; OPTIMIZATION; PARALLEL ARCHITECTURES; PIPELINE PROCESSING SYSTEMS; SILICON;

PARALLEL PROCESSING SYSTEMS;

EID: 84868706992     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/CGO.2006.11     Document Type: Conference Paper

References (24)

1. Press release: Intel silicon innovation to shape direction of the digital world: Multi-core processors, other key silicon technologies part of platform approach, Sept. 2004.
2. V. Bala, E. Duesterwald, and S. Banerjia. Dynamo: A transparent dynamic optimization system. In Proceedings of the ACM SIGPLAN Conference on Programming Language Design and Implementation, pages 1-12, June 2000.
3. T. Ball and J. R. Larus. Branch prediction for free. In Proceedings of the ACM SIGPLAN Conference on Programming Language Design and Implementation, pages 300-313, June 1993.
4. L. A. Barroso et al. Piranha: A scalable architecture based on single-chip multiprocessing. In Proceedings of the International Symposium on Computer Architecture, pages 282-293, June 2000.
5. D. Bhandarkar and J. Ding. Performance characterization of the Pentium Pro processor. In Proceedings of the International Symposium on High-Performance Computer Architecture, pages 288-297, Feb. 1997.
6. D. Bruening, T. Garnett, and S. Amarasinghe. An infrastructure for adaptive dynamic optimization. In Proceedings of the International Symposium on Code Generation and Optimization: Feedback-Directed and Runtime Optimization, pages 265-275, Mar. 2003.
7. J. F. Cantin and M. D. Hill. Cache performance for SPEC CPU2000 benchmarks: Version 3.0, 2003. http://www.cs.wisc.edu/multifacet/misc/ spec2000cachedata.
8. B. Cmelik and D. Keppel. Shade: A fast instruction-set simulator for execution profiling. In Proceedings of the ACM SIGMETRICS Conference on the Measurement and Modeling of Computer Systems, pages 128-137, May 1994.
9. J. C. Dehnert et al. The Transmetta code morphing software: Using speculation, recovery, and adaptive retranslation to address real-life challenges. In Proceedings of the International Symposium on Code Generation and Optimization, pages 15-24, Mar. 2003.
10. G. Desoli, N. Mateev, E. Duesterwald, P. Faraboschi, and J. A. Fisher. DELI: A new run-time control point. In Proceedings of the International Symposium on Microarchitecture, 2002.
11. K. Ebcioglu and E. R. Altman. DAISY: Dynamic compilation for 100% architectural compatibility. In Proceedings of the International Symposium on Computer Architecture, pages 26-37, June 1997.
12. M. Gschwind, E. R. Altman, S. Sathaye, P. Ledak, and D. Appenzeller. Dynamic and transparent binary translation. IEEE Computer, 33(3): 54-59, Mar. 2000.
13. A. KleinOsowski and D. J. Lilja. MinneSPEC: A new SPEC benchmark workload for simulation-based computer architecture research. Computer Architecture Letters, 1, June 2002.
14. K. Mai et al. Smart Memories: A modular reconfigurable architecture. In Proceedings of the International Symposium on Computer Architecture, pages 161-171, June 2000.
15. N. Nethercote and J. Seward. Valgrind: A program supervision framework. Electronic Notes in Theoretical Computer Science, 89(2), 2003.
16. K. Sankaralingam et al. Exploiting ILP, TLP, and DLP with the polymorphous TRIPS architecture. In Proceedings of the International Symposium on Computer Architecture, pages 422-433, June 2003.
17. H. Sharangpani and K. Arora. Itanium processor microarchitecture. IEEE Micro, 20(5): 24-43, Sept. 2000.
18. B. Slechta et al. Dynamic optimization of micro-operations. In Proceedings of the International Symposium on High- Performance Computer Architecture, pages 165-176, Feb. 2003.
19. S. Swanson, K. Michelson, A. Schwerin, and M. Oskin. Wavescalar. In Proceedings of the International Symposium on Microarchitecture, pages 291-302, Dec. 2003.
20. M. B. Taylor et al. The Raw microprocessor: A computational fabric for software circuits and general-purpose programs. IEEE Micro, 22(2): 25-35, Mar. 2002.
21. M. B. Taylor et al. Evaluation of the Raw microprocessor: An exposed-wire-delay architecture for ILP and streams. In Proceedings of the International Symposium on Computer Architecture, pages 2-13, June 2004.
22. J. Tendler, J. Dodson, J. J.S. Fields, H. Le, and B. Sinharoy. POWER4 system microarchitecture. IBM Journal of Research and Development, 46(1): 5-25, Jan. 2002.
23. M. Tremblay, J. Chan, S. Chaudhry, A. W. Conigliaro, and S. S. Tse. The MAJC architecture: a synthesis of parallelism and scalability. IEEE Micro, 20(6): 12-25, Nov. 2000.
24. E.Witchel and M. Rosenblum. Embra: Fast and flexible machine simulation. In Proceedings of the ACM SIGMETRICS International Conference on Measurement and Modeling of Computer Systems, pages 68-79, May 1996.