Scan-based speed-path debug for a microprocessor

IEEE Design and Test of Computers

Volumn 29, Issue 4, 2012, Pages 92-99

  Zeng, Jing ^a   Guo, Ruifeng ^b   Cheng, Wu Tung ^b   Mateja, Michael A ^c   Wang, Jing ^c  

^a APPLE INC   (United States)

^b MENTOR GRAPHICS CORPORATION   (United States)

^c ADVANCED MICRO DEVICES   (United States)

Author keywords

At speed test; Diagnosis; Silicon debug; Speed path debug; Timing failure

Indexed keywords

45NM TECHNOLOGY; AMD OPTERON; AT-SPEED; AT-SPEED TEST; ATPG TOOLS; FUNCTIONAL PATTERN; MULTITHREADED PROCESSORS; ON CHIPS; PARAMETRIC TEST; PATH DELAY; PATH DELAY FAULT; PATH SENSITIZATION; SCAN PATTERNS; SCAN TESTS; SILICON DEBUG; SPEED-PATH DEBUG;

DIAGNOSIS; INTEGRATED CIRCUIT TESTING;

SPEED;

EID: 84867805543     PISSN: 07407475     EISSN: None     Source Type: Journal    
DOI: 10.1109/MDT.2012.2208353     Document Type: Article

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