Path delay fault diagnosis in combinational circuits with implicit fault enumeration

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 20, Issue 10, 2001, Pages 1226-1235

  Pant, Pankaj ^a,b   Hsu, Yuan Chieh ^c   Gupta, Sandeep K ^a,d   Chatterjee, Abhijit ^a,e  

^a IEEE   (United States)

^b HEWLETT PACKARD COMPANY   (United States)

^c SYNOPSYS INC   (United States)

^d University of Southern California ^*  (United States)

^e GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

ATPG; Delay testing; Fault diagnosis; Testing

Indexed keywords

FAULT DIAGNOSIS;

ALGORITHMS; DATA STRUCTURES; DELAY CIRCUITS; INTEGRATED CIRCUIT TESTING;

COMBINATORIAL CIRCUITS;

EID: 0035472653     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/43.952739     Document Type: Article

References (13)

1. Effectiveness of a variable sampling time strategy for delay fault diagnosis
2. An advanced diagnostic method for delay faults in combinational faulty circuits
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5. A new path-oriented effect-cause methodology to diagnose delay failures
6. Efficient diagnosis of path delay faults in digital logic circuits
7. On delay fault testing in logic circuits
8. Generation of high quality tests for robustly untestable path delay faults
9. On variable clock methods for path delay testing of sequential circuits
10. Delay fault diagnosis in sequential circuits based on path-tracing
11. Scan latch design for delay test