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Volumn 150, Issue 5 SPEC. ISS., 2003, Pages 346-354

Delay defect diagnosis based upon a statistical timing model - The first step

Author keywords

[No Author keywords available]

Indexed keywords

DELAY DEFECTS; LOGIC DEFECTS; STATISTICAL TIMING MODELS;

EID: 0344496063     PISSN: 13502387     EISSN: None     Source Type: Journal    
DOI: 10.1049/ip-cdt:20030834     Document Type: Conference Paper
Times cited : (6)

References (17)
  • 2
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    • New validation and test problems for high performance deep sub-micron VLSI circuits
    • Tutorial notes, April
    • Breuer, M.A., Gleason, C., and Gupta, S.: 'New validation and test problems for high performance deep sub-micron VLSI circuits'. Tutorial notes, Presented at IEEE VLSI Test Symp., April 1997
    • (1997) IEEE VLSI Test Symp.
    • Breuer, M.A.1    Gleason, C.2    Gupta, S.3
  • 3
    • 0033221624 scopus 로고    scopus 로고
    • Nanometer technology effects on fault models for IC testing
    • Aitken, R.C.: 'Nanometer technology effects on fault models for IC testing', Comput., 1999, 32, pp. 46-51
    • (1999) Comput. , vol.32 , pp. 46-51
    • Aitken, R.C.1
  • 7
    • 0032181414 scopus 로고    scopus 로고
    • Location of stuck-at faults and bridging faults based on circuit partitioning
    • Pomeranz, I., and Reddy, S.M.: 'Location of stuck-at faults and bridging faults based on circuit partitioning', IEEE Trans. Comput., 1998, 47, pp. 1124-1135
    • (1998) IEEE Trans. Comput. , vol.47 , pp. 1124-1135
    • Pomeranz, I.1    Reddy, S.M.2
  • 10
    • 0032684766 scopus 로고    scopus 로고
    • A new method for diagnosing multiple stuck-at faults using multiple and single fault simulations
    • Takahashi, H., Boateng, K.O., and Takamatsu, Y.: 'A new method for diagnosing multiple stuck-at faults using multiple and single fault simulations'. Presented at 17th IEEE VLSI test Symp., 1999
    • (1999) 17th IEEE VLSI Test Symp.
    • Takahashi, H.1    Boateng, K.O.2    Takamatsu, Y.3
  • 12
    • 0034479212 scopus 로고    scopus 로고
    • Path-delay fault diagnosis in non-scan sequential circuits with at-speed test application
    • October
    • Pant, P., and Chatterjee, A.: 'Path-delay fault diagnosis in non-scan sequential circuits with at-speed test application'. Proc. IEEE Int. Test Conf., October 2000, pp. 245-252
    • (2000) Proc. IEEE Int. Test Conf. , pp. 245-252
    • Pant, P.1    Chatterjee, A.2
  • 14
    • 0033316674 scopus 로고    scopus 로고
    • Test generation for crosstalk-induced delay in integrated circuits
    • October
    • Chen, W.-Y., Gupta, S.K., and Breuer, M.A.: 'Test generation for crosstalk-induced delay in integrated circuits'. Proc. IEEE Int. Test Conf., October 1999, pp. 191-200
    • (1999) Proc. IEEE Int. Test Conf. , pp. 191-200
    • Chen, W.-Y.1    Gupta, S.K.2    Breuer, M.A.3
  • 16
    • 0036049286 scopus 로고    scopus 로고
    • False-path-aware statistical timing analysis and efficient path selection for delay testing and timing validation
    • June
    • Liou, J.-J., Krstic, A., Wang, L.-C., and Cheng, K.-T.: 'False-path-aware statistical timing analysis and efficient path selection for delay testing and timing validation'. Presented at Design automation Conf., June 2002
    • (2002) Design Automation Conf.
    • Liou, J.-J.1    Krstic, A.2    Wang, L.-C.3    Cheng, K.-T.4


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.