Energy efficiency analysis of GPUs

Proceedings of the 2012 IEEE 26th International Parallel and Distributed Processing Symposium Workshops, IPDPSW 2012

Volumn , Issue , 2012, Pages 1014-1022

  Cebrián, Juan M ^a   Guerrero, Ginés D ^a   García, José M ^a  

^a UNIVERSITY OF MURCIA   (Spain)

Author keywords

Energy Efficiency; GPGPU; GPU; Power Dissipation

Indexed keywords

BANDWIDTH REQUIREMENT; DATA DEPENDENCIES; DESIGN CHALLENGES; EFFICIENCY ANALYSIS; ENERGY EFFICIENT; GPGPU; GPU; GRAPHICS PROCESSING UNITS; LEGACY SOFTWARE; MASSIVELY PARALLEL COMPUTING; MEMORY WALL; NEW DESIGN; PARALLEL APPLICATION; POWER MANAGEMENTS; RESOURCE OPTIMIZATION;

COMPUTER GRAPHICS; DESIGN; DISTRIBUTED PARAMETER NETWORKS; ENERGY DISSIPATION; ENERGY EFFICIENCY; ENERGY MANAGEMENT; OPTIMIZATION; PARALLEL ARCHITECTURES;

PROGRAM PROCESSORS;

EID: 84867434965     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IPDPSW.2012.124     Document Type: Conference Paper

References (25)

1. H. Esmaeilzadeh, E. Blem, R. S. Amant, K. Sankaralingam, and D. Burger, "Dark silicon and the end of multicore scaling," in Proceedings of the 38th International Symposium on Computer Architecture, June 2011.
2. S. Huang, S. Xiao, and W. Feng, "On the energy efficiency of graphics processing units for scientific computing," in Proceedings of the 2009 IEEE International Symposium on Parallel&Distributed Processing, ser. IPDPS '09. Washington, DC, USA: IEEE Computer Society, 2009, pp. 1-8. [Online]. Available: http://dx.doi.org/10.1109/IPDPS.2009.5160980
3. W. B. Dally, "Power, programmability, and granularity: The challenges of exascale computing," in IEEE International Parallel & Distributed Processing Symposium Keynote, 2011.
4. P.-H. Wang, C.-L. Yang, Y.-M. Chen, and Y.-J. Cheng, "Power gating strategies on gpus," ACM Trans. Archit. Code Optim., vol. 8, pp. 13:1-13:25, October 2011. [Online]. Available: http://doi.acm.org/10.1145/ 2019608.2019612
5. S. Kaxiras and M. Martonosi, Computer Architecture Techniques for Power-Efficiency. Morgan and Claypool Publ., 2008.
6. P. Macken, M. Degrauwe, M. Van Paemel, and H. Oguey, "A voltage reduction technique for digital systems," in Proceedings of the 37th IEEE International Solid-State Circuits Conference. Digest of Technical Papers, 1990, pp. 238-239.
7. T. Simunic, L. Benini, A. Acquaviva, P. Glynn, and G. de Micheli, "Dynamic voltage scaling and power management for portable systems," in Proceedings on Design Automation Conference, 2001, pp. 524-529.
8. Q. Wu, P. Juang, M. Martonosi, and D. W. Clark, "Voltage and frequency control with adaptive reaction time in multipleclock-domain processors," in Proceedings of the 11th International Symposium on High-Performance Computer Architecture, 2005, pp. 178-189.
9. M. J. Flynn and P. Hung, "Microprocessor design issues: Thoughts on the road ahead," vol. 25, no. 3, pp. 16-31, 2005.
10. A. et al. Keshavarzi, "Intrinsic iddq: Origins, reduction, and applications in deep sub- low-power cmos ic's," in Proceedings of the IEEE International Test Conference, 1997.
11. N. S. Kim, T. Austin, D. Baauw, T. Mudge, K. Flautner, J. S. Hu, M. J. Irwin, M. Kandemir, and V. Narayanan, "Leakage current: Moore's law meets static power," Computer, vol. 36, no. 12, pp. 68-75, 2003.
12. C. Zander, "Clock manipulation on fermi and newer gpus. website: http://www.phoronix.com/scan.php?page=news item&px=otgxnq."
13. A. CHANDRAKASAN and R. RODERSEN, Low Power CMOS Design. IEEE Press, 1998.
14. A. P. Chandrakasan, W. J. Bowhill, and F. Fox, Design of High-Performance Microprocessor Circuits, 1st ed. Wiley-IEEE Press, 2000.
15. M. Powell, S.-H. Yang, B. Falsafi, K. Roy, and T. N. Vijaykumar, "Gated-vdd: A circuit technique to reduce leakage in deep-submicron cache memories," in Proceedings of the International Symposium on Low Power Electronics and Design, 2000.
16. A. Iyer, "Demystify power gating and stop leakage cold. website: http://www.powermanagementdesignline.com/howto/181500691."
17. Z. Hu, A. Buyuktosunoglu, V. Srinivasan, V. Zyuban, H. Jacobson, and P. Bose, "Microarchitectural techniques for power gating of execution units," in Proceedings of the 2004 international symposium on Low power electronics and design, ser. ISLPED '04. New York, NY, USA: ACM, 2004, pp. 32-37. [Online]. Available: http://doi.acm.org/10.1145/1013235.1013249
18. S. Hong and H. Kim, "An integrated gpu power and performance model," in Proceedings of the 37th annual international symposium on Computer architecture, ser. ISCA '10. New York, NY, USA: ACM, 2010, pp. 280-289. [Online]. Available: http://doi.acm.org/10.1145/1815961.1815998
19. J. W. Sheaffer, D. Luebke, and K. Skadron, "A flexible simulation framework for graphics architectures," in Proceedings of the ACM SIGGRAPH/EUROGRAPHICS conference on Graphics hardware, ser. HWWS '04, 2004.
20. R. Fu, A. Zhai, P. chung Yew, and W. chung Hsu, "Reducing queuing stalls caused by data prefetching," 2007.
21. Y. Wang and N. Ranganathan, "An instructionlevel energy estimation and optimization methodology for gpu," in Proceedings of the 2011 IEEE 11th International Conference on Computer and Information Technology, ser. CIT '11. Washington, DC, USA: IEEE Computer Society, 2011, pp. 621-628. [Online]. Available: http://dx.doi.org/10.1109/CIT.2011.69
22. "Wattup .net power meter. website: https://www.wattsupmeters.com/. "
23. "Msi afterburner overclocking tool. website: http://event.msi.com/ vga/afterburner/index.htm."
24. "Cuda sdk. website: http://developer.nvidia.com/gpucomputing-sdk. "
25. A. Kerr, G. Diamos, and S. Yalamanchili, "A characterization and analysis of ptx kernels," in Proceedings of the 2009 IEEE International Symposium on Workload Characterization (IISWC), ser. IISWC '09. Washington, DC, USA: IEEE Computer Society, 2009, pp. 3-12. [Online]. Available: http://dx.doi.org/10.1109/IISWC.2009.5306801