Power gating strategies on GPUs

Transactions on Architecture and Code Optimization

Volumn 8, Issue 3, 2011, Pages

  Wang, Po Han ^a   Yang, Chia Lin ^a   Chen, Yen Ming ^a   Cheng, Yu Jung ^a  

^a NATIONAL TAIWAN UNIVERSITY   (Taiwan)

Author keywords

GPU; Leakage; Power gating

Indexed keywords

CLOCK GATING; DYNAMIC POWER REDUCTION; DYNAMIC VOLTAGE AND FREQUENCY SCALING; EXECUTION UNITS; GPU; GRAPHICS PROCESSING UNIT; IDLE TIME; LEAKAGE REDUCTION; LOW POWER; PERFORMANCE DEGRADATION; POWER GATING; POWER GATINGS; POWER-GATING MECHANISMS; TIME-OUTS; WORKLOAD VARIATION;

BUFFER STORAGE; ENERGY EFFICIENCY; GEOMETRY; MICROPROCESSOR CHIPS;

PROGRAM PROCESSORS;

EID: 80455130016     PISSN: 15443566     EISSN: 15443973     Source Type: Journal    
DOI: 10.1145/2019608.2019612     Document Type: Article

References (44)

1. AKENINE-MOLLER, T. AND STROM, J. 2003. Graphics for the masses: a hardware rasterization architecture for mobile phones. In Proceedings of the ACM SIGGRAPH International Conference on Computer Graphics and Interactive Techniques (SIGGRAPH'03). ACM, New York, NY, 801-808
2. ANTOCHI, I., JUURLINK, B., VASSILIADIS, S., AND LIUHA, P. 2004. Scene management models and overlap tests for tile-based rendering. In Proceedings of the EUROMICRO Symposium on Digital System Design (DSD'04). IEEE Computer Society, 424-431 (Pubitemid 40266706)
3. BEYOND3D. 2008. Ati rv635 chip details. http://www.beyond3d.com/ resources/chip/127
4. BORKAR, S. 1999. Design challenges of technology scaling. IEEE Micro 19, 4, 23-29
5. BUTLER, H. 2010. Nvidia geforce gtx 480 1,536mb review. http://www.bittech.net/hardware/2010/03/27/nvidiageforce- gtx-480-1-5gb-review/ 10
6. CEBENOYAN, C. 2004. Graphics pipeline performance. In GPU Gems: Programming Techniques, Tips and Tricks for Real-Time Graphics, R. Fernando, Ed., Pearson Higher Education, Chapter 28, 473-486
7. CHANDRAKASAN, A., BOWHILL, W. J., AND FOX, F. 2000. Design of High-Performance Microprocessor Circuits. Wiley-IEEE Press
8. CHEN, M., STOLL, G., IGEHY, H., PROUDFOOT, K., AND HANRAHAN, P. 1998. Simple models of the impact of overlap in bucket rendering. In Proceedings of the ACM SIGGRAPH/EUROGRAPHICS Workshop on Graphics Hardware (HWWS'98). ACM, New York, NY, 105-112
9. CLAYPOOL, K. AND CLAYPOOL, M. 2007. On frame rate and player performance in first person shooter games. Springer Multimedia Syst. J. 13, 1, 3-17 (Pubitemid 47150829)
10. COX, M. AND BHANDARI, N. 1997. Architectural implications of hardware-accelerated bucket rendering on the pc. In Proceedings of the ACM SIGGRAPH/EUROGRAPHICS Workshop on Graphics Hardware. ACM, New York, NY, 25-34
11. DEL BARRIO, V. M., GONZALEZ, C., ROCA, J., FERNANDEZ, A. 2006. Attila: a cycle-level executiondriven simulator for modern GPU architectures. In Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS'06). IEEE Computer Society, 231-241 (Pubitemid 44711127)
12. DUARTE, D., TSAI, Y-F., VIJAYKRISHNAN, N., AND IRWIN, M. J. 2002. Evaluating run-time techniques for leakage power reduction. In Proceedings of the Conference on Asia South Pacific Design Automation/VLSI Design (ASPDAC'02). IEEE Computer Society, 31-38
13. FLAUTNER, K, KIM, N. S., MARTIN, S., BLAAUW, D., AND MUDGE, T. 2002. Drowsy caches: Simple techniques for reducing leakage power. In Proceedings of the 29th Annual International Symposium on Computer Architecture (ISCA'02). IEEE Computer Society, 148-157 (Pubitemid 34691858)
14. GOODHEAD, P. 2010. Matrix hd 5870 power consumption and thermals. http://www.bittech.net/hardware/graphics/2010/07/15/asus-matrix-hd-5870- graphics-card-review/7
15. GU, Y. AND CHAKRABORTY, S. 2008a. Control theory-based DVS for interactive 3d games. In Proceedings of the 45th Annual Conference on Design Automation (DAC'08). ACM, New York, NY, 740-745
16. GU, Y. AND CHAKRABORTY, S 2008b. A hybrid DVS scheme for interactive 3d games. In Proceedings of the IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS'08). IEEE Computer Society, 3-12
17. GU, Y., CHAKRABORTY, S, AND OOI, W. T. 2006. Games are up for DVFs. In Proceedings of the 43rd Annual Conference on Design Automation (DAC'06). ACM, New York, NY, 598-603 (Pubitemid 47113966)
18. HONG, S. AND KIM, H. 2010. An integrated gpu power and performance model. In Proceedings of the 37th Annual International Symposium on Computer Architecture (ISCA'10). ACM, New York, NY, 280-289
19. HU, Z., BUYUKTOSUNOGLU, A., SRINIVASAN, V., ZYUBAN, V., JACOBSON, H., AND BOSe, P. 2004. Microarchitectural techniques for power gating of execution units. In Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED'04). ACM, New York, NY, 32-37 (Pubitemid 40454678)
20. IGEHY, H., ELDRIDGE, M., AND PROUDFOOT, K. 1998. Prefetching in a texture cache architecture. In HWWS'98: Proceedings of the ACM SIGGRAPH/EUROGRAPHICS Workshop on Graphics Hardware. ACM, New York, NY, 133-ff
21. ITRS. 2006. International technology roadmap for semiconductors
22. IYER, A. 2006. Demystify power gating and stop leakage cold. http://www.eetimes.com/design/automotivedesign/4012054/Demystif'y-power-gating- and-stop-leakage-cold
23. JUANG, P.,SKADRON, K.,MARTONOSI, M.,HU, Z.,CLARK, D.W.,DIODATO, P.W., AND KAXIRAS, S. 2004. Implementing branch-predictor decay using quasi-static memory cells. ACM Trans. Archit. Code Optim. 1, 2, 180-219
24. KALLA, P., HU, X. S., AND HENKEL, J. 2006. Distance-based recent use (dru): an enhancement to instruction cache replacement policies for transition energy reduction. IEEE Trans. VLSI Syst. 14, 1, 69-80
25. KANTER, D. 2008. Nvidia's gt200: Inside a parallel processor. http://www.realworldtech.com/page.cfm?ArticleID=RWT090808195242
26. KAO, J. AND CHANDRAKASAN, A. 2000. Dual-threshold voltage techniques for low-power digital circuits. IEEE J. Solid-State Circ. 35, 7, 1009-1018
27. KAXIRAS, S., HU, Z., AND MARTONOSI, M. 2001. Cache decay: exploiting generational behavior to reduce cache leakage power. In Proceedings of the 28th Annual International Symposium on Computer Architecture (ISCA'01). ACM, New York, NY, 240-251 (Pubitemid 32825409)
28. KHRONOS. 2010. Opencl overview. http://www.khronos.org/opencl/
29. LINDHOLM, E. AND OBERMAN, S. 2007. Nvidia geforce 8800 gpu. In Hot Chips 19: A Symposium on High Performance Chips
30. LU, Y.-H. AND MICHELI, G. D. 2001. Comparing system-level power management policies. IEEE Des. Test 18, 2, 10-19 (Pubitemid 32293324)
31. MANTOR,M. 2007. Radeon r600, a 2nd generation unified shader architecture. In Hot Chips 19: A Symposium on High Performance Chips
32. MOCHOCKI, B., LAHIRI, K, AND CADAMBI, S. 2006a. Power analysis of mobile 3d graphics. In Proceedings of the Conference on Design, Automation and Test in Europe (DATE'06). European Design and Automation Association, Belgium, 502-507
33. MOCHOCKI, B., LAHIRI, K, CADAMBI, S., AND HU, X. S. 2006b. Signature-based workload estimation for mobile 3d graphics. In Proceedings of the 43rd Annual Conference on Design Automation (DAC'06). ACM, New York, NY, 592-597 (Pubitemid 47113965)
34. NAM, B.-G., LEE, J.,KIM, K, LEE, S. J., AND YOO,H.-J. 2007. A low-power handheld GPU using logarithmic arithmetic and tripleDVFS power domains. In Proceedings of the 22nd ACM SIGGRAPH/EUROGRAPHICS Symposium on Graphics hardware (GH'07). 73-80
35. NVIDIA. 2010. Cuda zone. http://www.nvidia.com/object/cuda.home.new.html
36. POWELL, M., YANG, S.-H., FALSAFI, B., ROY, K., AND VIJAYKUMAR, T. N. 2000. Gated-vdd: A circuit technique to reduce leakage in deep-sub micron cache memories. In Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED'00). ACM, New York, NY, 90-95
37. SANDER, P. V., NEHAB, D., AND BARCZAK, J. 2007. Fast triangle reordering for vertex locality and reduced overdraw. ACM Trans. Graph. 26, 3, 89
38. SHEAFFER, J. W., LUEBKE, D., AND SKADRON, K. 2004. A flexible simulation framework for graphics architectures. In Proceedings of the ACM SIGGRAPH/EUROGRAPHICS conference on Graphics hardware (HWWS'04). ACM, New York, NY, 85-94
39. SHEAFFER, J. W., SKADRON, K., AND LUEBKE, D. P. 2005. Studying thermal management for graphicsprocessor architectures. In Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS'05). IEEE Computer Society, 54-65 (Pubitemid 43804303)
40. SOHN, J.-H., WOO, J.-H., LEE, M.-W., KIM, H.-J., WOO, R., AND YOO, H.-J. 2006. A 155-mw 50-m vertices/s graphics processor with fixed-point programmable vertex shader for mobile applications. IEEE J. Solid- State Circ. 41, 5, 1081-1091
41. SPILLE, C., VÖtter, R., AND SAUTER, M. 2010. Geforce gtx 480 and gtx 470 reviewed: Fermi performance benchmarks. http://www.pcgameshardware.comlaid. 743498/Geforce-GTX-480-and-GTX-470-reviewed-Fermiperformance-benchmarkslReviews/
42. VOICU, A. 2008. Ati rv770 - architecture overview. http://www.rage3d. comlreviews/video/atirv770/architecture/
43. WANG, P.-H., CHEN, Y.-M., YANG, C.-L., AND CHENG, Y.-J. 2009. A predictive shutdown technique for gpu shader processors. IEEE Comput. Archit. Lett. 8, 9-12
44. YOUSSEF, A., ANIS, M., AND ELMASRY, M. 2006. Dynamic standby prediction for leakage tolerant microprocessor functional units. In Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture. IEEE Computer Society, 371-384.