Fast extraction of high-frequency parallel admittance of Through-Silicon-Vias and their capacitive coupling-noise to active regions

IEEE MTT-S International Microwave Symposium Digest

Volumn , Issue , 2012, Pages

  Xu, Chuan ^a   Suaya, Roberto ^b   Banerjee, Kaustav ^a  

^a University of California   (United States)

^b MENTOR GRAPHICS CORPORATION   (United States)

Author keywords

3 D ICs; Extraction; Interconnect; Parallel admittance; Quasi electrostatic; Scalar potential Green's function; Through silicon via

Indexed keywords

3-D ICS; INTERCONNECT; QUASI-ELECTROSTATIC; SCALAR POTENTIAL; THROUGH-SILICON-VIA;

CAPACITANCE; ELECTRONICS PACKAGING; ELECTROSTATICS; EXTRACTION; FINITE ELEMENT METHOD; GREEN'S FUNCTION; INTEGRATED CIRCUITS; SEMICONDUCTING SILICON;

MATRIX ALGEBRA;

EID: 84866781930     PISSN: 0149645X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/MWSYM.2012.6259706     Document Type: Conference Paper

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