CCP: Common case promotion for improved timing error resilience with energy efficiency

Proceedings of the International Symposium on Low Power Electronics and Design

Volumn , Issue , 2012, Pages 135-140

  Wan, Lu ^a   Chen, Deming ^a  

^a UNIVERSITY OF ILLINOIS AT URBANA CHAMPAIGN   (United States)

Author keywords

Common case; Dynamic behavior; Probability; Resynthesis; Timing error resilience; Voltage overscaling

Indexed keywords

AREA OVERHEAD; CHARACTERISTIC FUNCTIONS; CIRCUIT DYNAMICS; CIRCUIT OPTIMIZATION; CORRECTION MECHANISM; DESIGN METHODOLOGY; DYNAMIC BEHAVIORS; INTERNAL STRUCTURE; LOGIC SYNTHESIS; NEW DESIGN; OPTIMIZATION CONVERGENCE; OVERALL ENERGY EFFICIENCY; RELIABILITY GUARANTEE; RESYNTHESIS; SIGNAL PROBABILITY; TIMING ERRORS; VOLTAGE OVERSCALING;

ELECTRIC NETWORK ANALYSIS; ENERGY EFFICIENCY; ENERGY UTILIZATION; ERROR CORRECTION; LOGIC DESIGN; LOW POWER ELECTRONICS; PROBABILITY;

TIMING CIRCUITS;

EID: 84865564506     PISSN: 15334678     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/2333660.2333695     Document Type: Conference Paper

References (17)

1. T. Austin, et al., "Opportunities and challenges for better than worst-case design", In Proceedings of ASP-DAC, 2005
2. D. Ernst, et al., "Razor: A Low-Power Pipeline Based on Circuit-Level Timing Speculation", Annual Intl. Symp. on MICRO, 2003.
3. K. Bowman, et al., "Circuit techniques for dynamic variation tolerance", In Proceedings of DAC, 2009.
4. R.A. Abdallah and N.R. Shanbhag, "Minimum-Energy Operation Via Error Resiliency," IEEE Embedded Systems Letters, vol.2, no. 4, pp.115-118, Dec. 2010
5. A. B. Kahng, et al., "Slack Redistribution for Graceful Degradation Under Voltage Overscaling", In Proceedings of ASP-DAC, 2010.
6. B. Greskamp, et al., "Blueshift: Designing processors for timing speculation from the ground up", In Proceedings of HPCA, 2009.
7. L. Wan and D. Chen, "DynaTune: Circuit-Level Optimization for Timing Speculation Considering Dynamic Path Behavior", In Proceedings of ICCAD, 2009.
8. J. Cong and K. Minkovich,"Logic Synthesis for Better Than Worst-case Designs", In Proceedings of VLSI-DAT, 2009.
9. S. Ghosh, et al., "A new paradigm for low-power, variation-tolerant circuit synthesis using critical path isolation", In Proceedings of ICCAD, 2006.
10. G. D. Micheli, "Synthesis and optimization of digital circuits", McGraw-Hill. 1994
11. Y. Kuo, et al., "Efficient Boolean characteristic function for fast timed ATPG", In Proceedings of ICCAD, 2006.
12. G. Silva, et al., "Satisfiability models and algorithms for circuit delay computation", ACM Trans. DAES, 2002.
13. Berkeley Logic Synthesis and Verification Group, "ABC: A System for Sequential Synthesis and Verification", Release 70930.
14. Niklas Eén, Niklas Sörensson: "An Extensible SAT-solver", In Proceedings of SAT, 2003.
15. A. Mishchenko, "An Introduction to Zero-Suppressed Binary Decision", In Proceedings of Calculemus 2001.
16. P.R. Menon, et al., "Redundancy Removal and Simplification of Combinational Circuits", In Proceedings of VLSI Test Symp., 1991.
17. C, Wu, et al., "SAT-Controlled Redundancy Addition and Removal - A Novel Circuit Restructuring Technique", In Proceedings of DAC 2009