SAT-Controlled redundancy addition and removal- A novel circuit restructuring technique

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Volumn , Issue , 2009, Pages 191-196

  Wu, Chi An ^a   Lin, Ting Hao ^a   Huang, Shao Lun ^a   Huang, Chung Yang ^a  

^a NATIONAL TAIWAN UNIVERSITY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

BOOLEAN CONSTRAINTS; BOOLEAN SATISFIABILITY; DECISION PROCEDURES; QUALITY PROBLEMS; RE-STRUCTURING TECHNIQUES; RUN-TIME;

BOOLEAN FUNCTIONS; DIGITAL INTEGRATED CIRCUITS; QUALITY ASSURANCE; REDUNDANCY;

COMPUTER AIDED DESIGN;

EID: 64549134608     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASPDAC.2009.4796479     Document Type: Conference Paper

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