메뉴 건너뛰기




Volumn , Issue , 2006, Pages 96-99

Efficient boolean characteristic function for fast timed ATPG

Author keywords

[No Author keywords available]

Indexed keywords

AUTOMATIC TEST PATTERN GENERATION; BOOLEAN FUNCTIONS; DESIGN; ELECTRIC CURRENTS; ELECTRIC NETWORK ANALYSIS; FUNCTION EVALUATION; NETWORKS (CIRCUITS); TIME MEASUREMENT; VECTORS;

EID: 46149117047     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICCAD.2006.320071     Document Type: Conference Paper
Times cited : (12)

References (18)
  • 5
    • 46149092442 scopus 로고    scopus 로고
    • A Timed Calculus for ATG-Based Timing Analysis of Circuits with Complex Gates
    • J. L. Güntzel, A. C. M. Pinto, and R. Reis "A Timed Calculus for ATG-Based Timing Analysis of Circuits with Complex Gates," in Proc. IEEE Latin American Test Workshop, pp. 234-239,2001.
    • (2001) Proc. IEEE Latin American Test Workshop , pp. 234-239
    • Güntzel, J.L.1    Pinto, A.C.M.2    Reis, R.3
  • 6
    • 0029358733 scopus 로고
    • Pattern Independent Maximum Current Estimation in Power and Ground Buses of CMOS VLSI Circuits: Algorithms, Signal Correlations, and Their Resolution
    • Aug
    • H. Kriplani, F Najm, and I. N. Hajj, "Pattern Independent Maximum Current Estimation in Power and Ground Buses of CMOS VLSI Circuits: Algorithms, Signal Correlations, and Their Resolution," IEEE Trans. on Computer-Aided Design, vol. 14, no. 8, pp. 998-1012, Aug. 1995.
    • (1995) IEEE Trans. on Computer-Aided Design , vol.14 , Issue.8 , pp. 998-1012
    • Kriplani, H.1    Najm, F.2    Hajj, I.N.3
  • 7
    • 0034135572 scopus 로고    scopus 로고
    • Estimation for Maximum Instantaneous Current Through Supply Lines for CMOS Circuits
    • Feb
    • Y.-M. Jiang, A. Krstic, and K.-T. Cheng, "Estimation for Maximum Instantaneous Current Through Supply Lines for CMOS Circuits," IEEE Trans. on Very Large Scale Integration Systems, vol. 8, no. 1, pp. 61-73, Feb. 2000.
    • (2000) IEEE Trans. on Very Large Scale Integration Systems , vol.8 , Issue.1 , pp. 61-73
    • Jiang, Y.-M.1    Krstic, A.2    Cheng, K.-T.3
  • 9
    • 0142206125 scopus 로고    scopus 로고
    • Timed Test Generation for Crosstalk Switch Failure in Domino CMOS Circuits
    • R. Kundu, and R. D. Blanton, "Timed Test Generation for Crosstalk Switch Failure in Domino CMOS Circuits," in Proc. of the IEEE VLSI Test Symposium, pp. 379-385,2002.
    • (2002) Proc. of the IEEE VLSI Test Symposium , pp. 379-385
    • Kundu, R.1    Blanton, R.D.2
  • 10
    • 0346148426 scopus 로고    scopus 로고
    • ATPG for Noise-Induced Switch Failures in Domino Logic
    • R. Kundu, and R. D. Blanton, "ATPG for Noise-Induced Switch Failures in Domino Logic," in Proc. of the 1CCAD, pp. 765-768, 2003.
    • (2003) Proc. of the 1CCAD , pp. 765-768
    • Kundu, R.1    Blanton, R.D.2
  • 13
    • 26444437950 scopus 로고    scopus 로고
    • Backtrack Search Algorithms for Propositional Satisfiability: Review and Innovations,
    • Master's Thesis, the Hebrew University of Jerusalem
    • A. Nadel, "Backtrack Search Algorithms for Propositional Satisfiability: Review and Innovations," Master's Thesis, the Hebrew University of Jerusalem, 2002.
    • (2002)
    • Nadel, A.1
  • 15
    • 0032680865 scopus 로고    scopus 로고
    • GRASP: A Search Algorithm for Propositional Satisfiability
    • May
    • J. P. M. Silva, and K. A. Sakallah, "GRASP: A Search Algorithm for Propositional Satisfiability," IEEE Trans. on Computers, vol. 48, no. 5, pp. 506-521, May 1999.
    • (1999) IEEE Trans. on Computers , vol.48 , Issue.5 , pp. 506-521
    • Silva, J.P.M.1    Sakallah, K.A.2
  • 17
    • 0029488471 scopus 로고
    • Hierarchical Timing Analysis Using Conditional Delays
    • H. Yalcin, and J. P. Hayes, "Hierarchical Timing Analysis Using Conditional Delays," in Proc. of the ICCAD, pp. 371-377, 1995.
    • (1995) Proc. of the ICCAD , pp. 371-377
    • Yalcin, H.1    Hayes, J.P.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.