-
1
-
-
0029357465
-
Functional Timing Analysis Using ATPG
-
Aug
-
P. Ashar, and S. Malik, "Functional Timing Analysis Using ATPG," IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 14, no. 8, pp. 1025-1030, Aug. 1995.
-
(1995)
IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems
, vol.14
, Issue.8
, pp. 1025-1030
-
-
Ashar, P.1
Malik, S.2
-
2
-
-
0028124073
-
Timing Analysis of Combinational Circuits using ADD's
-
R. I. Bahar, H. Cho, G. D. Hachtel, E. Macii, and F. Somenzi, "Timing Analysis of Combinational Circuits using ADD's," in Proc. of IEEE European Design Test Conference, pp. 625-629, 1994.
-
(1994)
Proc. of IEEE European Design Test Conference
, pp. 625-629
-
-
Bahar, R.I.1
Cho, H.2
Hachtel, G.D.3
Macii, E.4
Somenzi, F.5
-
3
-
-
0027544793
-
Path Sensitization in Critical Path Problem
-
Feb
-
H.-C. Chen, and D. Du, "Path Sensitization in Critical Path Problem," IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 12, no. 2, pp. 196-207, Feb. 1993.
-
(1993)
IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems
, vol.12
, Issue.2
, pp. 196-207
-
-
Chen, H.-C.1
Du, D.2
-
4
-
-
0027849390
-
Computation of Floating Mode Delay in Combinational Circuits: Theory and Algorithms
-
Dec
-
S. Devadas, K. Keutzer, and S. Malik, "Computation of Floating Mode Delay in Combinational Circuits: Theory and Algorithms," IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 12, no. 12, pp. 1913-1923, Dec. 1993.
-
(1993)
IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems
, vol.12
, Issue.12
, pp. 1913-1923
-
-
Devadas, S.1
Keutzer, K.2
Malik, S.3
-
6
-
-
0029358733
-
Pattern Independent Maximum Current Estimation in Power and Ground Buses of CMOS VLSI Circuits: Algorithms, Signal Correlations, and Their Resolution
-
Aug
-
H. Kriplani, F Najm, and I. N. Hajj, "Pattern Independent Maximum Current Estimation in Power and Ground Buses of CMOS VLSI Circuits: Algorithms, Signal Correlations, and Their Resolution," IEEE Trans. on Computer-Aided Design, vol. 14, no. 8, pp. 998-1012, Aug. 1995.
-
(1995)
IEEE Trans. on Computer-Aided Design
, vol.14
, Issue.8
, pp. 998-1012
-
-
Kriplani, H.1
Najm, F.2
Hajj, I.N.3
-
7
-
-
0034135572
-
Estimation for Maximum Instantaneous Current Through Supply Lines for CMOS Circuits
-
Feb
-
Y.-M. Jiang, A. Krstic, and K.-T. Cheng, "Estimation for Maximum Instantaneous Current Through Supply Lines for CMOS Circuits," IEEE Trans. on Very Large Scale Integration Systems, vol. 8, no. 1, pp. 61-73, Feb. 2000.
-
(2000)
IEEE Trans. on Very Large Scale Integration Systems
, vol.8
, Issue.1
, pp. 61-73
-
-
Jiang, Y.-M.1
Krstic, A.2
Cheng, K.-T.3
-
8
-
-
0030655539
-
Estimation of Maximum Power and Instantaneous Current Using a Genetic Algorithm
-
Y.-M. Jiang, K.-T. Cheng, and A. Krstic, "Estimation of Maximum Power and Instantaneous Current Using a Genetic Algorithm," in Proc. of IEEE Custom Integrated Circuits Conference, pp. 135-138, 1997.
-
(1997)
Proc. of IEEE Custom Integrated Circuits Conference
, pp. 135-138
-
-
Jiang, Y.-M.1
Cheng, K.-T.2
Krstic, A.3
-
9
-
-
0142206125
-
Timed Test Generation for Crosstalk Switch Failure in Domino CMOS Circuits
-
R. Kundu, and R. D. Blanton, "Timed Test Generation for Crosstalk Switch Failure in Domino CMOS Circuits," in Proc. of the IEEE VLSI Test Symposium, pp. 379-385,2002.
-
(2002)
Proc. of the IEEE VLSI Test Symposium
, pp. 379-385
-
-
Kundu, R.1
Blanton, R.D.2
-
10
-
-
0346148426
-
ATPG for Noise-Induced Switch Failures in Domino Logic
-
R. Kundu, and R. D. Blanton, "ATPG for Noise-Induced Switch Failures in Domino Logic," in Proc. of the 1CCAD, pp. 765-768, 2003.
-
(2003)
Proc. of the 1CCAD
, pp. 765-768
-
-
Kundu, R.1
Blanton, R.D.2
-
11
-
-
0027061384
-
Timing Analysis and Delay-Fault Test Generation using Path-Recursive Functions
-
P. C. McGeer, A. Saldanha, P. R. Stephan, R. K. Brayton, and A. L. Sangiovanni-Vicentelli, "Timing Analysis and Delay-Fault Test Generation using Path-Recursive Functions," in Proc. of the 1CCAD, pp. 180-183, 1991.
-
(1991)
Proc. of the 1CCAD
, pp. 180-183
-
-
McGeer, P.C.1
Saldanha, A.2
Stephan, P.R.3
Brayton, R.K.4
Sangiovanni-Vicentelli, A.L.5
-
12
-
-
0034852165
-
Chaff: Engineering an efficient SAT solver
-
M. W. Moskewicz, C. F Madigan, Y. Zhao, L. Zhang, and S. Malik, "Chaff: Engineering an efficient SAT solver." in Proc. of the DAC, pp. 530-535, 2001.
-
(2001)
Proc. of the DAC
, pp. 530-535
-
-
Moskewicz, M.W.1
Madigan, C.F.2
Zhao, Y.3
Zhang, L.4
Malik, S.5
-
13
-
-
26444437950
-
Backtrack Search Algorithms for Propositional Satisfiability: Review and Innovations,
-
Master's Thesis, the Hebrew University of Jerusalem
-
A. Nadel, "Backtrack Search Algorithms for Propositional Satisfiability: Review and Innovations," Master's Thesis, the Hebrew University of Jerusalem, 2002.
-
(2002)
-
-
Nadel, A.1
-
15
-
-
0032680865
-
GRASP: A Search Algorithm for Propositional Satisfiability
-
May
-
J. P. M. Silva, and K. A. Sakallah, "GRASP: A Search Algorithm for Propositional Satisfiability," IEEE Trans. on Computers, vol. 48, no. 5, pp. 506-521, May 1999.
-
(1999)
IEEE Trans. on Computers
, vol.48
, Issue.5
, pp. 506-521
-
-
Silva, J.P.M.1
Sakallah, K.A.2
-
16
-
-
0036354804
-
Satisfiability Models and Algorithms for Circuit Delay Computation
-
Jan
-
L. G. Silva, J. P. M. Silva, L. M. Silveira, and K. A. Sakallah, "Satisfiability Models and Algorithms for Circuit Delay Computation," ACM Trans. on Design Automation of Electronic Systems, vol. 7, no. 1, pp. 137-158, Jan. 2002.
-
(2002)
ACM Trans. on Design Automation of Electronic Systems
, vol.7
, Issue.1
, pp. 137-158
-
-
Silva, L.G.1
Silva, J.P.M.2
Silveira, L.M.3
Sakallah, K.A.4
-
17
-
-
0029488471
-
Hierarchical Timing Analysis Using Conditional Delays
-
H. Yalcin, and J. P. Hayes, "Hierarchical Timing Analysis Using Conditional Delays," in Proc. of the ICCAD, pp. 371-377, 1995.
-
(1995)
Proc. of the ICCAD
, pp. 371-377
-
-
Yalcin, H.1
Hayes, J.P.2
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