-
1
-
-
77957012605
-
Parameter Variation Tolerance and Error Resiliency: New Design Paradigm for the Nanoscale Era
-
Oct.
-
S. Ghosh, et al., "Parameter Variation Tolerance and Error Resiliency: New Design Paradigm for the Nanoscale Era," Proc. IEEE, Vol.98, No.10, pp.1718-1751, Oct. 2010.
-
(2010)
Proc. IEEE
, vol.98
, Issue.10
, pp. 1718-1751
-
-
Ghosh, S.1
-
2
-
-
36949001469
-
An Analysis of Efficient Multi-Core Global Power Management Policies: Maximizing Performance for a Given Power Budget
-
C. Isci, et al., "An Analysis of Efficient Multi-Core Global Power Management Policies: Maximizing Performance for a Given Power Budget," Proc. MICRO, pp.347-358, 2006.
-
(2006)
Proc. MICRO
, pp. 347-358
-
-
Isci, C.1
-
3
-
-
84865541890
-
-
[Online]. Available
-
ITRS [Online]. Available: http://public.itrs.net
-
-
-
-
4
-
-
34548854756
-
A Distributed Critical-Path Timing Monitor for a 65nm High-Performance Microprocessor
-
A. Drake, et al., "A Distributed Critical-Path Timing Monitor for a 65nm High-Performance Microprocessor," Proc. ISSCC, pp. 398-399, 2007.
-
(2007)
Proc. ISSCC
, pp. 398-399
-
-
Drake, A.1
-
6
-
-
84858769317
-
Active Management of Timing Guardband to Save Energy in POW-ER7
-
C. R. Lefurgy, et al., "Active Management of Timing Guardband to Save Energy in POW-ER7," Proc. MICRO, 2011.
-
Proc. MICRO, 2011
-
-
Lefurgy, C.R.1
-
7
-
-
47349093600
-
Mitigating Parameter Variation with Dynamic Fine-Grain Body Biasing
-
R. Teodorescu, et al., "Mitigating Parameter Variation with Dynamic Fine-Grain Body Biasing," Proc. MICRO, pp. 27-42, 2007.
-
(2007)
Proc. MICRO
, pp. 27-42
-
-
Teodorescu, R.1
-
8
-
-
84862068210
-
Analysis of Instruction-level Vulnerability to Dynamic Voltage and Temperature Variations
-
A. Rahimi, et al., "Analysis of Instruction-level Vulnerability to Dynamic Voltage and Temperature Variations," Proc. DATE, pp.1102-1105, 2012.
-
(2012)
Proc. DATE
, pp. 1102-1105
-
-
Rahimi, A.1
-
9
-
-
80053284892
-
Resilient Architectures via Collaborative Design: Maximizing Commodity Processor Performance in the Presence of Variations
-
Oct.
-
V.J. Reddi, et al., "Resilient Architectures via Collaborative Design: Maximizing Commodity Processor Performance in the Presence of Variations," IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, Vol.30, No.10, pp.1429-1445, Oct. 2011.
-
(2011)
IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems
, vol.30
, Issue.10
, pp. 1429-1445
-
-
Reddi, V.J.1
-
10
-
-
78650896343
-
Within-Die Variation-Aware Dynamic-Voltage-Frequency-Scaling with Optimal Core Allocation and Thread Hopping for the 80-Core TeraFLOPS Processor
-
Jan.
-
S. Dighe, et al., "Within-Die Variation-Aware Dynamic-Voltage- Frequency-Scaling With Optimal Core Allocation and Thread Hopping for the 80-Core TeraFLOPS Processor," IEEE J. of Solid-State Circuits, Vol.46, No.1, pp. 184-193, Jan. 2011.
-
(2011)
IEEE J. of Solid-State Circuits
, vol.46
, Issue.1
, pp. 184-193
-
-
Dighe, S.1
-
11
-
-
84865541886
-
Variability-Aware Task Allocation for Energy-Efficient Quality of Service Provisioning in Embedded Streaming Multimedia Applications
-
F. Paterna, et al., "Variability-Aware Task Allocation for Energy-Efficient Quality of Service Provisioning in Embedded Streaming Multimedia Applications," IEEE Trans. on Computers, 2011.
-
(2011)
IEEE Trans. on Computers
-
-
Paterna, F.1
-
12
-
-
70350048928
-
Adaptive Idleness Distribution for Non-Uniform Aging Tolerance in MultiProcessor Systems-on-Chip
-
F. Paterna, et al., "Adaptive Idleness Distribution for Non-Uniform Aging Tolerance in MultiProcessor Systems-on-Chip," Proc. DATE, pp. 906-909, 2009.
-
(2009)
Proc. DATE
, pp. 906-909
-
-
Paterna, F.1
-
13
-
-
44149092485
-
A power supply selector for energy- And area-efficient local dynamic voltage scaling
-
S. Miermont, et al., "A power supply selector for energy- and area-efficient local dynamic voltage scaling," Proc. PATMOS, 2007.
-
Proc. PATMOS, 2007
-
-
Miermont, S.1
-
14
-
-
80052600775
-
History-Based Dynamic Voltage Scaling with Few Number of Voltage Modes for GALS NoC
-
A. Rahimi, et al., "History-Based Dynamic Voltage Scaling with Few Number of Voltage Modes for GALS NoC," Proc. FutureTech, 2010.
-
Proc. FutureTech, 2010
-
-
Rahimi, A.1
-
15
-
-
66749121858
-
Facelift: Hiding and Slowing Down Aging in Multicores
-
A. Tiwari, et al., "Facelift: Hiding and Slowing Down Aging in Multicores," Proc. MICRO, pp.129-140, 2008.
-
(2008)
Proc. MICRO
, pp. 129-140
-
-
Tiwari, A.1
-
16
-
-
76749156251
-
The BubbleWrap many-core: Popping cores for sequential acceleration
-
U.R. Karpuzcu, et al., "The BubbleWrap many-core: Popping cores for sequential acceleration," Proc. MICRO, pp.447-458, 2009.
-
(2009)
Proc. MICRO
, pp. 447-458
-
-
Karpuzcu, U.R.1
-
17
-
-
16244391007
-
Microarchitectural Simulation and Control of di/dt-induced Power Supply Voltage Variation
-
E. Grochowski, et al., "Microarchitectural Simulation and Control of di/dt-induced Power Supply Voltage Variation," Proc. HPCA, pp. 7-16, 2002.
-
(2002)
Proc. HPCA
, pp. 7-16
-
-
Grochowski, E.1
-
18
-
-
16244397252
-
Control Techniques to Eliminate Voltage Emergencies in High-Performance Processors
-
R. Joseph, et al., "Control Techniques to Eliminate Voltage Emergencies in High-Performance Processors," Proc. HPCA, pp. 79-90, 2003.
-
(2003)
Proc. HPCA
, pp. 79-90
-
-
Joseph, R.1
-
19
-
-
77954510740
-
Thermal-aware voltage droop compensation for multi-core architectures
-
J. Zhao, et al., "Thermal-aware voltage droop compensation for multi-core architectures," Proc. GLSVLSI, 2010.
-
Proc. GLSVLSI, 2010
-
-
Zhao, J.1
-
20
-
-
77954511970
-
Voltage Emergency Prediction: A Signature-Based Approach to Reducing Voltage Emergencies
-
V. Reddi, et al., "Voltage Emergency Prediction: A Signature-Based Approach To Reducing Voltage Emergencies," Proc. HPCA, pp. 18-27, 2009.
-
(2009)
Proc. HPCA
, pp. 18-27
-
-
Reddi, V.1
-
21
-
-
16244412618
-
Eliminating Voltage Emergencies via Microarchitectural Voltag Control Feedback and Dynamic Optimization
-
K. Hazelwood, et al., "Eliminating Voltage Emergencies via Microarchitectural Voltag Control Feedback and Dynamic Optimization," Proc. ISLPED, pp. 326-331, 2004.
-
(2004)
Proc. ISLPED
, pp. 326-331
-
-
Hazelwood, K.1
-
23
-
-
83755163724
-
Exploring instruction caching strategies for tightly-coupled shared-memory clusters
-
D. Bortolotti, et al., "Exploring instruction caching strategies for tightly-coupled shared-memory clusters," Proc. Int. Sym. on SoC, pp. 34-41, 2011.
-
(2011)
Proc. Int. Sym. on SoC
, pp. 34-41
-
-
Bortolotti, D.1
-
24
-
-
78650861417
-
A 45 nm Resilient Microprocessor Core for Dynamic Variation Tolerance
-
Jan.
-
K. Bowman, et al. "A 45 nm Resilient Microprocessor Core for Dynamic Variation Tolerance," IEEE J. of Solid-State Circuits, Vol.46, No.1, pp.194-208, Jan. 2011.
-
(2011)
IEEE J. of Solid-State Circuits
, vol.46
, Issue.1
, pp. 194-208
-
-
Bowman, K.1
-
25
-
-
80053505095
-
A Fully-Synthesizable Single-Cycle Interconnection Network for Shared-L1 Processor Clusters
-
A. Rahimi, et al., "A Fully-Synthesizable Single-Cycle Interconnection Network for Shared-L1 Processor Clusters," Proc. DATE, pp.1-6, 2011.
-
(2011)
Proc. DATE
, pp. 1-6
-
-
Rahimi, A.1
-
26
-
-
63449116547
-
An Asynchronous Power Aware and Adaptive NoC Based Circuit
-
April
-
E. Beigne, et al., "An Asynchronous Power Aware and Adaptive NoC Based Circuit," IEEE J. of Solid-State Circuits, Vol.44, No.4, pp.1167-1177, April 2009.
-
(2009)
IEEE J. of Solid-State Circuits
, vol.44
, Issue.4
, pp. 1167-1177
-
-
Beigne, E.1
-
29
-
-
84865541891
-
-
Available
-
LEON3 [Online]. Available: http://www.gaisler.com/cms/
-
LEON3 [Online]
-
-
|