TapeCache: A high density, energy efficient cache based on domain wall memory

Proceedings of the International Symposium on Low Power Electronics and Design

Volumn , Issue , 2012, Pages 185-190

  Venkatesan, Rangharajan ^a   Kozhikkottu, Vivek ^a   Augustine, Charles ^b   Raychowdhury, Arijit ^b   Roy, Kaushik ^a   Raghunathan, Anand ^a  

^a PURDUE UNIVERSITY   (United States)

^b INTEL CORPORATION   (United States)

Author keywords

cache; domain wall memory; spin memory

Indexed keywords

ACCESS LATENCY; AVERAGE ENERGY; CACHE; CACHE ORGANIZATION; CO-DESIGNS; ENERGY EFFICIENT; FERROMAGNETIC WIRES; GENERAL-PURPOSE COMPUTING; HIGH DENSITY; HIGH ENERGY EFFICIENCY; MANAGEMENT POLICY; MEMORY TECHNOLOGY; MULTI-PORT; NON-VOLATILE MEMORIES; PERFORMANCE IMPROVEMENTS; PERFORMANCE PENALTIES; READ OPERATION; READ/WRITE CHARACTERISTICS; SPIN MEMORIES;

BENCHMARKING; DESIGN; DYNAMIC RANDOM ACCESS STORAGE; ENERGY EFFICIENCY; LOW POWER ELECTRONICS; MACROS; MRAM DEVICES; STATIC RANDOM ACCESS STORAGE;

CACHE MEMORY;

EID: 84865546090     PISSN: 15334678     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/2333660.2333707     Document Type: Conference Paper

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