Energy efficient many-core processor for recognition and mining using spin-based memory

Proceedings of the 2011 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2011

Volumn , Issue , 2011, Pages 122-128

  Venkatesan, Rangharajan ^a   Chippa, Vinay K ^a   Augustine, Charles ^a   Roy, Kaushik ^a   Raghunathan, Anand ^a  

^a Purdue University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

45NM TECHNOLOGY; ARCHITECTURAL MODELS; ARCHITECTURAL TRADEOFFS; DATA-INTENSIVE WORKLOADS; DOMAIN SPECIFIC; ENERGY DELAY PRODUCT; ENERGY EFFICIENT; HIGH-DENSITY; K-MEANS CLUSTERING; MAGNETIC RAMS; MANY-CORE; MEMORY ACCESS; MEMORY SYSTEMS; MEMORY TECHNOLOGY; ON CHIP MEMORY; RANDOM ACCESS; SECOND LEVEL; SPIN MEMORIES; SPIN TRANSFER TORQUE; SPIN-BASED DEVICES;

DATA MINING; DESIGN; ENERGY EFFICIENCY; MAGNETIC DOMAINS; MAGNETIC STORAGE; MEMORY ARCHITECTURE; MRAM DEVICES; NANOSTRUCTURED MATERIALS; NANOTECHNOLOGY; PARALLEL ARCHITECTURES; PARALLEL PROCESSING SYSTEMS;

RANDOM ACCESS STORAGE;

EID: 79961181353     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/NANOARCH.2011.5941493     Document Type: Conference Paper

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