Design exploration of hybrid caches with disparate memory technologies

Transactions on Architecture and Code Optimization

Volumn 7, Issue 3, 2010, Pages

  Wu, Xiaoxia ^a   Li, Jian ^b   Zhang, Lixin ^b   Speight, Evan ^b   Rajamony, Ram ^b   Xie, Yuan ^a  

^a The Pennsylvania State University   (United States)

^b IBM AUSTIN RESEARCH LABORATORY   (United States)

Author keywords

Cache hierarchy; Embedded DRAM; Hybrid cache architecture; Magnetic RAM; Nonuniform cache architecture; Phase change RAM; Power; Thermal; Three dimensional IC design

Indexed keywords

CACHE ARCHITECTURE; CACHE HIERARCHIES; EMBEDDED DRAM; IC DESIGNS; MAGNETIC RAMS; NON-UNIFORM CACHE ARCHITECTURE; PHASE-CHANGE RAM; POWER; THERMAL;

DESIGN; DYNAMIC RANDOM ACCESS STORAGE; MICROPROCESSOR CHIPS; STATIC RANDOM ACCESS STORAGE; TECHNOLOGY; THREE DIMENSIONAL;

CACHE MEMORY;

EID: 78651380668     PISSN: 15443566     EISSN: 15443973     Source Type: Journal    
DOI: 10.1145/1880037.1880040     Document Type: Article

References (48)

1. ABABEI, C., FENG, Y., GOPLEN, B., MOGAL, H., ZHANG, T., BAZARGAN, K., AND SAPATNEKAR, S. S. 2005. Placement and routing in 3D integrated circuits. IEEE Design Test Comput. 22, 6, 520-531.
2. ATWOOD, G. AND BEZ, R. 2005. Current status of chalcogenide phase change memory. In Device Research Conference Digest., Vol. 1, 29-33.
3. BADER, D. A., LI, Y., LI, T., AND SACHDEVA, V. 2005. BioPerf: A benchmark suite to evaluate highperformance computer architecture on bioinformatics applications. In Proceedings of the IEEE International Symposium on Workload Characterization. 163-173.
4. BAILEY, D., BARTON, J., LASINSKI, T., AND SIMON, H. 1991. The NAS parallel benchmarks. Tech. rep. RNR-91-002 revision2. 453-464.
5. BECKMANN, B.M. ANDWOOD, D. A. 2004. Managing wire delay in large chip-multiprocessor caches. In Proceedings of the International Symposium on Microarchitecture. IEEE Computer Society, Los Alamitos, CA, 319-330.
6. BEDESCHI, F.,BONIZZONI, E.,CASAGRANDE, G.,GASTALDI, R.,RESTA, C.,TORELLI, G., AND ZELLA, D. 2005. SET and RESET pulse characterization in BJT-selected phase-change memories. In Proceedings of the IEEE International Symposium on Circuits and Systems. Vol. 2, 1270-1273.
7. BIENIA, C., KUMAR, S., SINGH, J. P., AND LI, K. 2008. The PARSEC benchmark suite: Characterization and architectural implications. In Proceedings of the 17th International Conference on Parallel Architectures and Compilation Techniques. ACM, New York, NY, 72-81.
8. BOHRER, P.,PETERSON, J.,ELNOZAHY,M.,RAJAMONY, R.,GHEITH, A.,ROCKHOLD, R.,LEFURGY, C.,SHAFI, H., NAKRA, T., SIMPSON, R., SPEIGHT, E., SUDEEP, K.,HENSBERGEN, E. V., AND ZHANG, L. 2004. Mambo: A full system simulator for the powerpc architecture. SIGMETRICS Perform. Eval. Rev. 31, 4, 8-12.
9. BROOKS, D., TIWARI, V., AND MARTONOSI, M. 2000. Wattch: A framework for architectural-level power analysis and optimizations. In Proceedings of the International Symposium on Computer Architecture. ACM, New York, NY, 83-94.
10. BRYAN, B., MURALI, A., NED, B., JOHN, D., LEI, J., GABRIEL, H. L., DON, M., PAT, M., DONALD, W. N., DANIEL, P., PAUL, R., JEFF, R., SADASIVAN, S., JOHN, S., AND CLAIR, W. 2006. Die stacking (3D) microarchitecture. In Proceedings of the International Symposium on Microarchitecture. IEEE Computer Society, Los Alamitos, CA, 469-479.
11. CHEN, Y., RETTNER, C., RAOUX, S., BURR, G., CHEN, S., SHELBY, R., SALINGA, M., RISK, W., HAPP, T., MCCLELLAND, G., BREITWISCH, M., SCHROTT, A., PHILIPP, J., LEE, M., CHEEK, R.,NIRSCHL, T., LAMOREY, M., CHEN, C., JOSEPH, E., ZAIDI, S.,YEE, B.,LUNG, H.,BERGMANN, R., AND LAM, C. 2006. Ultra-thin phase-change bridge memory device using GeSb. In Proceedings of the International Electron Devices Meeting, 1-4.
12. CHISHTI, Z., POWELL, M. D., AND VIJAYKUMAR, T. N. 2003. Distance associativity for highperformance energy-efficient non-uniform cache architectures. In Proceedings of the International Symposium on Microarchitecture. 55-64.
13. CHISHTI, Z., POWELL, M. D., AND VIJAYKUMAR, T. N. 2005. Optimizing replication, communication, and capacity allocation in CMPs. SIGARCH Comput. Archit. News 33, 2, 357-368.
14. CHUNG, L. 2008. Cell design considerations for phase change memory as a universal memory. In Proceedings of the International Symposium on VLSI Technology, Systems and Applications. 132-133.
15. 2 memory cell. J. Appl. Phys. 94, 5, 3536-3542.
16. DAVIS,W. R.,WILSON, J.,MICK, S.,XU, J.,HUA, H.,MINEO, C.,SULE, A. M.,STEER, M., AND FRANZON, P. D. 2005. Demystifying 3D ICs: The pros and cons of going vertical. IEEE Desi. Test Comput. 22, 6, 498-510.
17. DONG, X., WU, X., SUN, G., XIE, Y., LI, H., AND CHEN, Y. 2008. Circuit and microarchitecture evaluation of 3D stacking magnetic RAM (MRAM) as a universal memory replacement. In Proceedings of the Design Automation Conference. 554-559.
18. DONG, X. AND XIE, Y. 2009. System-level cost analysis and design exploration for threedimensional integrated circuits (3D ICs). In Proceedings of the Asia and South Pacific Design Automation Conference. IEEE Los Alamitos, CA, NJ, 234-241.
19. FLAUTNER, K., KIM, N. S., MARTIN, S., BLAAUW, D., AND MUDGE, T. 2002. Drowsy caches: Simple techniques for reducing leakage power. SIGARCH Comput. Archit. News 30, 2, 148-157.
20. GHOSH, M. AND LEE, H.-H. S. 2007. Smart refresh: An enhanced memory controller design for reducing energy in conventional and 3D die-stacked DRAMs. In Proceedings of the International Symposium on Microarchitecture. 134-145.
21. HANZAWA, S., KITAI, N., OSADA, K., KOTABE, A., MATSUI, Y., MATSUZAKI, N., TAKAURA, N., MONIWA, M., AND KAWAHARA, T. 2007. A 512KB embedded phase change memory with 416kB/s write throughput at 100uA cell write current. In Proceedings of the IEEE International Solid-State Circuits Conference. 474-616.
22. HOSOMI, M., YAMAGISHI, H., YAMAMOTO, T., ET AL. 2005. A novel nonvolatile memory with spin torque transfer magnetization switching: Spin-RAM. In Proceedings of the International Electron Devices Meeting. 459-462.
23. HUANG, W., SANKARANARAYANAN, K., SKADRON, K., RIBANDO, R., AND STAN, M. 2008. Accurate, pre- RTL temperature-aware design using a parameterized, geometric thermal model. IEEE Trans. Comput. 57, 9, 1277-1288.
24. HUH, J.,KIM, C., SHAFI, H., ZHANG, L.,BURGER, D., AND KECKLER, S.W. 2005. A NUCA substrate for flexible CMP cache sharing. In Proceedings of the International Conference on Supercomputing. 31-40.
25. IACOBOVICI, S., SPRACKLEN, L., KADAMBI, S., CHOU, Y., AND ABRAHAM, S. G. 2004. Effective streambased and execution-based data prefetching. In Proceedings of the International Conference on Supercomputing. 1-11.
26. JOUPPI, N. 1990. Improving direct-mapped cache performance by the addition of a small fullyassociative cache and prefetch buffers. In Proceedings of the International Symposium on Computer Architecture., 364-373.
27. JOYNER, J. W. AND MEINDL, J. D. 2002. Opportunities for reduced power dissipation using three-dimensional integration. In Proceedings of the Interconnect Technology Conference. 148-150.
28. KAWAHARA, T., TAKEMURA, R., MIURA, K., AND ET AL. 2007. 2Mb Spin-transfer torque RAM (SPRAM) with bit-by-bit bidirectional current write and parallelizing-direction current read. In Proceedings of the IEEE International Solid-State Circuits Conference. 480-617.
29. KGIL, T., D'SOUZA, S., SAIDI, A., BINKERT, N., DRESLINSKI, R.,MUDGE, T., REINHARDT, S., AND FLAUTNER, K. 2006. PicoServer: Using 3D stacking technology to enable a compact energy efficient chip multiprocessor. SIGARCH Comput. Archit. News 34, 5, 117-128.
30. KIM, C.,BURGER, D., AND KECKLER, S.W. 2002. An adaptive, non-uniform cache structure for wiredelay dominated on-chip caches. In Proceedings of the International Conference on Architectural Support for Programming Languages and Operating Systems. 211-222.
31. LEE, B. C., IPEK, E., MUTLU, O., AND BURGER, D. 2009. Architecting phase change memory as a scalable DRAM alternative. In Proceedings of the 36th International Symposium on Computer Architecture. 2-13.
32. LI, F., NICOPOULOS, C., RICHARDSON, T., XIE, Y., NARAYANAN, V., AND KANDEMIR, M. 2006. Design and management of 3D chip multiprocessors using network-in-memory. In Proceedings of the International Symposium on Computer Architecture 34, 2, 130-141. (Pubitemid 46016610)
33. LIU, C., GANUSOV, I., BURTSCHER, M., AND TIWARI, S. 2005. Bridging the processor-memory performance gap with 3D IC technology. IEEE Des. Test Comput. 22, 6, 556-564.
34. LOH, G. H. 2008. 3D-stacked memory architectures for multi-core processors. In Proceedings of the International Symposium on Computer Architecture. 453-464.
35. MADAN, N., ZHAO, L., MURALIMANOHAR, N., UDIPI, A., BALASUBRAMONIAN, R., IYER, R., MAKINENI, S., AND NEWELL, D. 2009. Optimizing communication and capacity in a 3D stacked reconfigurable cache hierarchy. In Proceedings of the IEEE International Symposium on High Performance Computer Architecture, 262-274.
36. MANGALAGIRI, P., SARPATWARI, K.,YANAMANDRA, A.,NARAYANAN, V.,XIE, Y., IRWIN, M. J., AND KARIM, O. A. 2008. A low-power phase change memory based hybrid cache architecture. In Proceedings of the Great Lakes Symposium on VLSI. 395-398.
37. MORIN, R., KUMAR, A., AND ILYINA, E. 2005. A multi-level comparative performance characterization of SPECjbb2005 Versus SPECjbb2000. In Proceedings of the IEEE International Workload Characterization. 67-75.
38. MURALIMANOHAR, N., BALASUBRAMONIAN, R., AND JOUPPI, N. 2007. Optimizing NUCA organizations and wiring alternatives for large caches with CACTI 6.0. In Proceedings of the 40th Annual IEEE/ACMInternational Symposium on Microarchitecture. IEEE Computer Society, Los Alamitos, CA, 3-14.
39. PELLIZZER, F., PIROVANO, A., OTTOGALLI, F., MAGISTRETTI, M., SCARAVAGGI, M., ZULIANI, P., TOSI, M., BENVENUTI, A., BESANA, P., CADEO, S.,MARANGON, T.,MORANDI, R., PIVA, R., SPANDRE, A., ZONCA, R., MODELLI, A.,VARESI, E.,LOWREY, T.,LACAITA, A.,CASAGRANDE, G.,CAPPELLETTI, P., AND BEZ, R. 2004. Novel utrench phase-change memory cell for embedded and stand-alone non-volatile memory applications. In Proceedings of the Symposium on VLSI Technology. 18-19.
40. QURESHI, M. K., SRINIVASAN, V., AND RIVERS, J. A. 2009. Scalable high performance main memory system using phase-change memory technology. In Proceedings of the 36th International Symposium on Computer Architecture. 24-33.
41. SINHAROY, B., KALLA, R. N., TENDLER, J. M., EICKEMEYER, R. J., AND JOYNER, J. B. 2005. Power5 system microarchitecture. IBM J. Resear. Devel. 49, 4/5, 505-521.
42. SPEC. 2006. Standard Performance Evaluation Corporation. http://www.spec.org/cpu2006/.
43. SUN, G.,DONG, X.,XIE, Y., LI, J., AND CHEN, Y. 2009. A novel architecture of the 3D stacked MRAM L2 cache for CMPs. In Proceedings of the IEEE International Symosium on High Performance Computer Architecture. 239-249.
44. WOO, S. C., OHARA, M., TORRIE, E., SINGH, J. P., AND GUPTA, A. 1995. The SPLASH-2 programs: Characterization and methodological considerations. SIGARCH Comput. Archit. News 23, 2, 24-36.
45. WU, X., LI, J., ZHANG, L., SPEIGHT, E., AND XIE, Y. 2009. Power and performance of read-write aware hybrid caches with non-volatile memories. In Proceedings of the Conference on Design, Automation and Test in Europe. 737-742.
46. XIE, Y., LOH, G. H., BLACK, B., AND BERNSTEIN, K. 2006. Design space exploration for 3D architectures. J. Emerg. Technol. Comput. Syst. 2, 2, 65-10
47. ZHAO, W., BELHAIRE, E., MISTRAL, Q., CHAPPERT, C., JAVERLIAC, V., DIENY, B., AND NICOLLE, E. 2006. Macro-model of spin-transfer torque based magnetic tunnel junction device for hybrid magnetic-CMOS design. In Proceedings of the IEEE International Behavioral Modeling and Simulation Workshop. 40-43.
48. ZHOU, P., ZHAO, B., YANG, J., AND ZHANG, Y. 2009. A durable and energy efficient main memory using phase change memory technology. In Proceedings of the 36th International Symposium on Computer Architecture. 14-23.