Thermal characterization of bare-die stacked modules with Cu through-vias

Proceedings - Electronic Components and Technology Conference

Volumn , Issue , 2001, Pages 730-737

  Yamaji, Y ^a   Ando, T ^a   Morifuji, T ^a   Tomisaka, M ^a   Sunohara, M ^a  

^a ASSOCIATION OF SUPER ADVANCED ELECTRONICS TECHNOLOGIES ASET   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

COPPER; DIES; HEAT RESISTANCE; INTERFACES (MATERIALS); PRODUCT DESIGN; PRODUCT DEVELOPMENT; THERMOANALYSIS; THERMODYNAMIC PROPERTIES; THREE DIMENSIONAL;

BARE DIE STACKED MODULES; LASER FLASH METHOD; PROCESS DEVELOPMENT; THERMAL BUMPS; THERMAL CONDUCTION ANALYSIS;

ELECTRONICS PACKAGING;

EID: 0034835759     PISSN: 05695503     EISSN: None     Source Type: Journal    
DOI: 10.1109/ECTC.2001.927813     Document Type: Article

References (9)

1. A review of 3-D packaging technology
2. Trends of three-dimensions packaging
3. 3D LSI stacking integration and wafer thinning technology
4. Interfacial thermal resistance - Method of measurement and impact of adhesive
5. Development of encapsulation for the plural narrow gaps of the three-dimensional stacked LSI
6. Flash method of determining thermal diffusivity, heat capacity and thermal conductivity
7. An analytical solution of temperature response in multilayered materials for transient methods
8. Analytical assessment on the effectiveness of thermal vias in cooling multichip modules
9. Thermal management estimations for buried bump interconnection technology printed wiring boards with bump (filled via) interconnection