Interface-state modeling of Al2O3–InGaAs MOS from depletion to inversion

IEEE Transactions on Electron Devices

Volumn 59, Issue 9, 2012, Pages 2383-2389

  Chen, Han Ping ^a,c   Yuan, Yu ^a,b   Yu, Bo ^a,b   Ahn, Jaesoo ^a,c   McIntyre, Paul C ^a,c   Asbeck, Peter M ^a,b   Rodwell, Mark J W ^a,d   Taur, Yuan ^a,b  

^a IEEE   (United States)

^b UNIVERSITY OF CALIFORNIA   (United States)

^c Stanford University   (United States)

^d University of California   (United States)

Author keywords

Bulk oxide trap; Dit; III V; Interface trap; MOS

Indexed keywords

CAPACITANCE; EQUIVALENT CIRCUITS; MOLYBDENUM;

BULK OXIDE TRAPS; FITTING OF DATA; FREQUENCY DEPENDENCE; GATE VOLTAGES; INTERFACE STATE DENSITY; INTERFACE TRAPS; MAJORITY CARRIERS; TIME CONSTANTS;

INTERFACE STATES;

EID: 84864031513     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2012.2205255     Document Type: Article

References (13)

1. 3 based ALD dielectric,” in Proc. 69th Annu. DRC, 2011, pp. 117–118.
2. xAs interfaces using capacitance–voltage and conductance methods,” Appl. Phys. Lett., vol. 94, no. 10, pp. 102 902-1–102 902-3, Mar. 2009.
3. S. Sioncke, H. C. Lin, L. Nyns, G. Brammertz, A. Delabie, T. Conard, A. Franquet, J. Rip, H. Struyf, S. D. Gendt, M. Muller, B. Beckhoff, and M. Caymax, “S-passivation of the Ge gate stack: Tuning the gate stack properties by changing the atomic layer deposition oxidant precursor,” J. Appl. Phys., vol. 110, no. 8, pp. 084907-1–084907-8, Oct. 2011.
4. 0.47As gate stacks,” J. Appl. Phys., vol. 108, no. 3, pp. 034111-1–034111-4, Aug. 2010.
5. 3 as gate insulator,” Microelectron. Eng., vol. 86, no. 7–9, pp. 1554–1557, Jul. 2009.
6. 0.47As interfaces: Experiment and simulation,” J. Appl. Phys., vol. 106, no. 12, pp. 124 508-1–124 508-8, Dec. 2009.
7. K. Martens, C. C. On, G. Brammertz, B. De Jaeger, D. Kuzum, M. Meuris, M. Heyns, T. Krishnamohan, K. Saraswat, H. E. Maes, and G. Groeseneken, “On the correct extraction of interface trap density of MOS devices with high-mobility semiconductor substrates,” IEEE Trans. Electron Devices, vol. 55, no. 2, pp. 547–556, Feb. 2008.
8. G. Brammertz, A. Alian, D. H. C. Lin, M. Meuris, M. Caymax, and W. E. Wang, “A combined interface and border trap model for high-mobility substrate metal–oxide–semiconductor devices applied to InGaAs and InP capacitors,” IEEE Trans. Electron Devices, vol. 58, no. 11, pp. 3890–3897, Nov. 2011.
9. E. H. Nicollian and J. R. Brews, MOS (Metal Oxide Semiconductor) Physics and Technology. New York: Wiley, 1982.
10. 0.47As (100) gate stacks and their passivation by hydrogen anneals,” Appl. Phys. Lett., vol. 96, no. 1, pp. 012906-1–012906-3, Jan. 2010.
11. TCAD Sentaurus Device User’s Manual, Synopsys Inc., Mountain View, CA, 2007.
12. 3 InGaAs MOS devices,” IEEE Trans. Electron Devices, vol. 59, no. 8, pp. 2100–2106, Aug. 2012.
13. Y. Yuan, “Non-classical MOSFETs: Design, modeling, and characterization,” Ph.D. dissertation, Elect. Eng. (Appl. Phys.), Univ. California, San Diego, CA, 2012.