Construction of constrained multi-bit flip-flops for clock power reduction

1st International Conference on Green Circuits and Systems, ICGCS 2010

Volumn , Issue , 2010, Pages 675-678

  Yan, Jin Tai ^a   Chen, Zhi Wei ^a  

^a CHUNG HUA UNIVERSITY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

BIT-FLIPS; CPU TIME; INPUT AND OUTPUTS; LENGTH CONSTRAINTS; MULTI-BITS; ORIGINAL DESIGN; POWER REDUCTIONS;

FLIP FLOP CIRCUITS;

EID: 77956602525     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICGCS.2010.5542978     Document Type: Conference Paper

References (8)

1. A. P. Chandrakasan and R. W. Brodersen, Low Power Digital CMOS Design, Kluwer Academic Publishers, 1995.
2. T. Sakurai, T. Kuroda, "Low-Power Circuit design for multimedia CMOS VLSI's." International Workshop on Synthesis and System Integration of Mixed Information technologies, pp. 3-10, 1996.
3. R. Lu, G. Zhong, C. Koh, and K. Chao, "Flip-flop and repeater insertion for early interconnect planning," Design Automation and Test in Europe, pp.690-695, 2002.
4. N. Akkiraju and M. Mohan, "Spec based flip-flop and buffer insertion," International Conference on Computer Design, pp.270-275, 2003.
5. L. Simonson, K. H. Tarn, N. Akkiraju, M. Mohan and L. He, "Leveraging delay slack in flip-flop and buffer insertion for power reduction" 5th International Symposium on Quality Electronic Design, 2004.
6. S. Y. Chen and T. C. Wang, "Blockage-aware routing tree construction with concurrent buffer and flip-flop insertion," International Workshop on Synthesis and System Integration of Mixed Information Technologies, pp. 147-154, 2007.
7. D. Duarte, V. Narayanan and M. J. Irwin, "Impact of technology scaling in the clock system power," IEEE Computer Society Annual Symposium on VLSI, 2002.
8. http://140.112.42.200/cad10/HTMLS/problems.html.