Power-state-aware buffered tree construction

26th IEEE International Conference on Computer Design 2008, ICCD

Volumn , Issue , 2008, Pages 21-26

  Jiang, Iris Hui Ru ^a   Wu, Ming Hua ^b  

^a NATIONAL CHIAO TUNG UNIVERSITY   (Taiwan)

^b REALTEK SEMICONDUCTOR CORP   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

SIGNAL PROCESSING; SYSTEMS ENGINEERING; TIMING CIRCUITS;

BUFFER INSERTIONS; HIERARCHICAL APPROACHES; INTERCONNECT DELAYS; LOWER-POWER CONSUMPTION; MULTIPLE SUPPLY VOLTAGES; NANO TECHNOLOGIES; POWER STATE; SIGNAL INTEGRITIES; SIGNAL-INTEGRITY PROBLEMS; TIMING CONSTRAINTS; TREE CONSTRUCTIONS;

WIRELESS TELECOMMUNICATION SYSTEMS;

EID: 62349093962     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICCD.2008.4751835     Document Type: Conference Paper

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