Power reduction via near-optimal library-based cell-size selection

Proceedings -Design, Automation and Test in Europe, DATE

Volumn , Issue , 2011, Pages 867-870

  Rahman, Mohammad ^a   Tennakoon, Hiran ^a   Sechen, Carl ^a  

^a The University of Texas at Dallas   (United States)

Author keywords

delay modelling; discrete cell size selection; parallelism; power delay optimization

Indexed keywords

BRANCH-AND-BOUND ALGORITHMS; CELL-SIZE; DELAY MODELLING; DISCRETE CELL-SIZE SELECTION; DYNAMIC POWER; DYNAMIC POWER REDUCTION; GLOBAL MINIMIZATION; INDUSTRIAL DESIGN; LEAKAGE POWER; PARALLELISM; POWER REDUCTIONS; POWER-DELAY OPTIMIZATION; SIZE SELECTION; STANDARD CELL; TRANSISTOR SIZE;

ALGORITHMS; DESIGN; ELECTRIC BATTERIES; ION BEAMS; OPTIMIZATION;

DIGITAL LIBRARIES;

EID: 79957562268     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (8)

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