The compact modeling of channel potential in sub-30-nm NAND flash cell string

IEEE Electron Device Letters

Volumn 33, Issue 3, 2012, Pages 321-323

  Kang, Myounggon ^a,b   Lee, Kyunghwan ^a   Chae, Dong Hyuk ^a,b   Park, Byung Gook ^a   Shin, Hyungcheol ^a  

^a Seoul National University   (South Korea)

^b SAMSUNG Electronics   (South Korea)

Author keywords

BSIM4; channel potential; drain induced barrier lowering (DIBL); gate induced drain leakage (GIDL); junction leakage; nand Flash; nand string

Indexed keywords

BSIM4; CHANNEL POTENTIAL; DRAIN-INDUCED BARRIER LOWERING (DIBL); GATE-INDUCED DRAIN LEAKAGE (GIDL); JUNCTION LEAKAGE; NAND FLASH; NAND STRING;

CIRCUIT SIMULATION; DYNAMIC RANDOM ACCESS STORAGE; MODELS;

CYTOLOGY;

EID: 84862828279     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/LED.2011.2179283     Document Type: Article

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