MM11 based flash memory cell model including characterization procedure

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn , Issue , 2006, Pages 3518-3521

  Saillet, B ^a   Regnier, A ^a   Portal, J M ^b   Delsuc, B ^b   Laffont, R ^b   Masson, P ^b   Bouchakour, R ^b  

^a STMICROELECTRONICS   (France)

^b AIX MARSEILLE UNIVERSITÉ   (France)

Author keywords

[No Author keywords available]

Indexed keywords

CHARGE CARRIERS; CIRCUIT SIMULATION; ELECTRIC CURRENT CONTROL; MATHEMATICAL MODELS; MOS DEVICES;

FLOATING GATE POTENTIAL; PRAGMATIC MODELS;

FLASH MEMORY;

EID: 34547283497     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (8)

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3. E. Takeda, C. Y. Yang, A. M. Hamada, "Hot Carrier Effects in MOS Devices", New-York Academic, 1995.
4. D. Esseni, L. Selmi "A Better Understanding of Substrate Enhanced Gate Current in MOSFETs and Flash, Cells - Part I: Phenomenological Aspects", IEEE Trans. Electron Devices, Vol.46, p.369, February 1999.
5. L. Selmi, D. Esseni, "A Better Understanding of Substrate Enhanced Gate Current in MOSFETs and Plash Cells - Part II; Physical Analysis", IEEE Trans. Electron Devices, Vol.46, p.376, February 1999.
6. D. Esseni, L. Selmi, A. Ghetti, E. Sangiorgi, "Injection Efficiency of CHISEL Gate Currents in Short MOS Devices: Physical Mechanisms, Device Implications, and Sensitivity to Technological Parameters", IEEE Trans. Electron Devices, Vol.47, p.2.194, November 2000.
7. 2", Journal of Applied Physics, vol, 40, p. 278, 1969.
8. Y. Tsividis, "Operation and Modeling of the MOS transistor", Mc Graw Hill international Edition, 1999.