Modeling of Vth Shift in NAND flash-memory cell device considering crosstalk and short-channel effects

IEEE Transactions on Electron Devices

Volumn 55, Issue 4, 2008, Pages 1020-1026

  Jung, Sang Goo ^a   Lee, Keun Woo ^a   Kim, Ki Seog ^b   Shin, Seung Woo ^b   Lee, Seaung Suk ^b,c   Om, Jae Chul ^b   Bae, Gi Hyun ^b   Lee, Jong Ho ^b  

^a Kyungpook National University   (South Korea)

^b Hynix Semiconductor Inc   (South Korea)

^c Yonsei University   (South Korea)

Author keywords

Adjacent cell; Coupling ratio (CR); Crosstalk; Drain induced barrier lowering (DIBL); Flash; Interference; NAND; Short channel effect (SCE); Vth shift

Indexed keywords

COMPUTER SIMULATION; CROSSTALK; SIGNAL INTERFERENCE; THRESHOLD VOLTAGE;

CAPACITANCE COUPLING; DRAIN-INDUCED BARRIER LOWERING; SHORT-CHANNEL EFFECT;

FLASH MEMORY;

EID: 41949084170     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2008.916769     Document Type: Article

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