An architecture-level approach for mitigating the impact of process variations on extensible processors

Proceedings -Design, Automation and Test in Europe, DATE

Volumn , Issue , 2012, Pages 467-472

  Kamal, Mehdi ^a   Afzali Kusha, Ali ^a   Safari, Saeed ^a   Pedram, Massoud ^b  

^a UNIVERSITY OF TEHRAN   (Iran)

^b University of Southern California   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CUSTOM INSTRUCTION; EXTENSIBLE PROCESSORS; INSTRUCTION SET ARCHITECTURE; PERFORMANCE DEGRADATION; PERFORMANCE PENALTIES; PROPAGATION DELAYS; PROPOSED ARCHITECTURES; SELECTION METHODS;

COMPUTER ARCHITECTURE;

EID: 84862067315     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/date.2012.6176516     Document Type: Conference Paper

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