Statistical high-level synthesis under process variability

IEEE Design and Test of Computers

Volumn 26, Issue 4, 2009, Pages 78-87

  Xie, Yuan ^a   Chen, Yibo ^a  

^a The Pennsylvania State University   (United States)

Author keywords

Adders; Clocks; Delay; Design and test; Libraries; Logic gates; Parametric yield; Probability density function; Process variation; Statistical high level synthesis

Indexed keywords

CMOS PROCESSS; DEEP SUB-MICRON; DELAY; HIGH LEVEL SYNTHESIS; PARAMETRIC YIELD; POWER CONSUMPTION; PROCESS VARIABILITY; PROCESS VARIATION; RECENT PROGRESS; SOC DESIGNS; STATISTICAL HIGH-LEVEL SYNTHESIS; TRANSISTOR PARAMETERS;

LIBRARIES; LOGIC GATES; PROBABILISTIC LOGICS;

PROBABILITY DENSITY FUNCTION;

EID: 69949138485     PISSN: 07407475     EISSN: None     Source Type: Journal    
DOI: 10.1109/MDT.2009.85     Document Type: Article

References (12)

1. C. Kenyon et al., "Managing Process Variation in Intel's 45nm CMOS Technology," Intel Technology J., vol. 12, no. 2, 2008; http://www.intel.com/technology/itj/2008/v12i2/3-managing/1-abstract.htm.
2. A. Srivastava, D. Sylvester, and D. Blaauw, Statistical Analysis and Optimization for VLSI: Timing and Power, Springer, 2005.
3. P. Coussy and A. Morawiec, High-Level Synthesis: From Algorithm to Digital Circuit, Springer, 2008.
4. F. Wang, G. Sun, and Y. Xie, "A Variation Aware High Level Synthesis Framework," Proc. IEEE Design, Automation and Test in Europe Conf. (DATE 08), IEEE CS Press, 2008, pp. 1063-1068.
5. W.-L. Hung, X. Wu, and Y. Xie, "Guaranteeing Performance Yield in High-Level Synthesis," Proc. IEEE/ACM Int'l Conf. Computer-Aided Design (ICCAD 06), IEEE CS Press, 2006, pp. 303-309.
6. J. Jung and T. Kim, "Timing Variation-Aware High-Level Synthesis," Proc. IEEE/ACM Int'l Conf. Computer-Aided Design (ICCAD 07), IEEE CS Press, 2007, pp. 424-428.
7. Y. Chen, J. Ouyang, and Y. Xie, "ILP-Based Scheme for Timing Variation-Aware Scheduling and Resource Binding," Proc. IEEE Int'l SOC Conf., IEEE Press, 2008, pp. 17-30.
8. F. Wang, A. Takach, and Y. Xie, "Variation-Aware Resource Sharing and Binding in Behavioral Synthesis," Proc. Conf. Asia and South Pacific Design Automation (ASP-DAC 09), IEEE Press, 2009, pp. 79-84.
9. G. Lucas, S. Cromar, and D. Chen, "FastYield: Variation-Aware, Layout-Driven Simultaneous Binding and Module Selection for Performance Yield Optimization," Proc. Conf. Asia and South Pacific Design Automation (ASP-DAC 09), IEEE Press, 2009, pp. 61-66.
10. Y. Chen and Y. Xie, "Tolerating Process Variations in High-Level Synthesis Using Transparent Latches," Proc. Conf. Asia and South Pacific Design Automation (ASP-DAC 09), IEEE Press, 2009, pp. 73-78.
11. W. Yang, I. Park, and C. Kyung, "Low-Power High-Level Synthesis Using Latches," Proc. Conf. Asia and South Pacific Design Automation (ASP-DAC 01), ACM Press, 2001, pp. 462-466.
12. F. Wang, X. Wu, and Y. Xie, "Variability-Driven Module Selection with Joint Design Time Optimization and Post-Silicon Tuning," Proc. Conf. Asia and South Pacific Design Automation (ASP-DAC 08), IEEE CS Press, 2008, pp. 2-9.