Double-soi wafer-bonded CMUTs with improved electrical safety and minimal roughness of dielectric and electrode surfaces

Journal of Microelectromechanical Systems

Volumn 21, Issue 3, 2012, Pages 668-680

  Zhang, Peiyu ^a   Fitzpatrick, Glen ^b   Harrison, Tyler ^a   Moussa, Walied A ^a   Zemp, Roger J ^a  

^a UNIVERSITY OF ALBERTA   (Canada)

^b Micralyne Inc   (Canada)

Author keywords

Addressable electrodes; dielectric charging; electrical safety; microelectromechanical systems (MEMS); micromachined transducers; silicon on insulator (SOI); ultrasound

Indexed keywords

1-D MODELS; ACTUATION TESTS; CAPACITIVE MICROMACHINED ULTRASOUND TRANSDUCER; CHARGE EFFECT; COMMERCIAL IMPLEMENTATION; DEVICE ARCHITECTURES; DEVICE FAILURES; DEVICE RELIABILITY; DEVICE SURFACES; DIELECTRIC CHARGING; DIELECTRIC SURFACE; ELECTRICAL SAFETY; ELECTRODE SURFACES; FABRICATION METHOD; FINITE-ELEMENT; FOWLER-NORDHEIM TUNNELING; HIGH VOLTAGE ELECTRODES; MICROMACHINED; SILICON ON INSULATOR WAFERS; SILICON-ON-INSULATORS; ULTRASOUND TRANSDUCERS;

DIELECTRIC DEVICES; ELECTRODES; ELECTROMECHANICAL DEVICES; MEMS; SURFACE ROUGHNESS; TRANSDUCERS; ULTRASONICS;

ULTRASONIC TRANSDUCERS;

EID: 84861858680     PISSN: 10577157     EISSN: None     Source Type: Journal    
DOI: 10.1109/JMEMS.2012.2189358     Document Type: Article

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