A 10-b 320-MS/s stage-gain-error self-calibration pipeline ADC

IEEE Journal of Solid-State Circuits

Volumn 47, Issue 6, 2012, Pages 1334-1343

  Tseng, Chien Jian ^a   Chen, Hung Wei ^a   Shen, Wei Ting ^a   Cheng, Wei Chih ^a   Chen, Hsin Shu ^a  

^a NATIONAL TAIWAN UNIVERSITY   (Taiwan)

Author keywords

Low gain opamp; pipeline analog to digital converter; self calibration; stage gain

Indexed keywords

ANALOG TO DIGITAL CONVERTERS; CALIBRATION CIRCUITS; CAPACITOR ARRAYS; CHIP AREAS; CLOCK CYCLES; CMOS TECHNOLOGY; CONVERSION RATES; DC GAIN; DIGITAL-TO-ANALOG CONVERTERS; GAIN ERRORS; LOW POWER; LOW-GAIN OPAMP; PIPELINE ADCS; REFERENCE SOURCE; SELF CALIBRATION; SELF-CALIBRATION TECHNIQUES; TOTAL POWER DISSIPATION;

CMOS INTEGRATED CIRCUITS; DC POWER TRANSMISSION; PIPELINES;

CALIBRATION;

EID: 84861725229     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2012.2192655     Document Type: Article

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