An over-60dB true rail-to-rail performance using correlated level shifting and an opamp with 30dB loop gain

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 51, Issue , 2008, Pages 540-542

  Gregoire, B Robert ^a   Moon, Un Ku ^a  

^a OREGON STATE UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

NETWORKS (CIRCUITS); SOLID STATE DEVICES;

LEVEL-SHIFTING; LOOP GAINS; PIPELINED ADCS; RAIL-TO-RAIL;

OPERATIONAL AMPLIFIERS;

EID: 49549084393     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2008.4523296     Document Type: Conference Paper

References (3)

1. A. M. Abo, P. R. Gray, "A 1.5-V, 10-bit, 14.3-MS/s CMOS Pipeline Analog-to-Digital Converter," IEEE J. Solid-State Circuits, vol.34, no.5, pp.599-606, May 1999.
2. C. C. Enz, G. C. Temes, "Circuit techniques for Reducing the Effects of Opamp Imperfections: Autozeroing, Correlated Double Sampling, and Chopper Stabilization," Proceedings of the IEEE, vol.84, no.11, pp.1584-1614, Nov 1996.
3. J. Li; U.-K. Moon, " A 1.8-V 67-mW 10-bit 100-MS/s Pipelined ADC Using Time-Shifted CDS Technique," IEEE J. Solid-State Circuits, vol.39, no.9, pp. 1468-1476, Sept. 2004.