A 10-Bit 500-MS/s 55-mW CMOS ADC

IEEE Journal of Solid-State Circuits

Volumn 44, Issue 11, 2009, Pages 3039-3050

  Verma, Ashutosh ^a   Razavi, Behzad ^b  

^a MARVELL SEMICONDUCTOR INC   (United States)

^b University of California   (United States)

Author keywords

Calibration by inverse function; Foreground digital calibration; Low gain op amp; Nonlinearity correction; Pipelined analog to digital converter; Resistor ladder DAC

Indexed keywords

FOREGROUND DIGITAL CALIBRATION; LOW GAIN OP AMP; NONLINEARITY CORRECTION; PIPELINED ANALOG-TO-DIGITAL CONVERTER; RESISTOR-LADDER DAC;

CMOS INTEGRATED CIRCUITS; DIGITAL INTEGRATED CIRCUITS; FREQUENCY CONVERTERS; LADDERS; MULTICARRIER MODULATION; RESISTORS;

CALIBRATION;

EID: 70449470435     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2009.2031044     Document Type: Article

References (21)

1. S. K. Gupta, M. A. Inerfield, and J.Wang, "A 1-GS/s 11-bit ADC with 55-dB SNDR, 250-mW power realized by a high bandwidth scalable time-interleaved architecture," IEEE J. Solid-State Circuits, vol.41, no.12, pp. 2650-2657, Dec. 2006.
2. C.-C. Hsu, F.-C. Huang, C.-Y. Shih, C.-C. Huang, Y.-H. Lin, C.-C. Leem, and B. Razavi, "An 11b 800 MS/s time-interleaved ADC with digital background calibration," in IEEE ISSCC Dig. Tech. Papers, 2007, pp. 464-465.
3. S.-C. Lee, Y.-D. Jeon, K.-D. Kim, J.-K. Kwon, J. Kim, J.-W. Moon, and W. Lee, "A 10b 205 MS/s 1 mm 90 nm CMOS pipeline ADC for flat-panel display applications," in IEEE ISSCC Dig. Tech. Papers, Feb. 2007, pp. 458-459.
4. K. Gulati, M. S. Peng, A. Pulinchery, C. E. Munoz, M. Lugin, A. R. Bugeja, J. Li, and A. P. Chandrakasan, "A highly integrated CMOS analog baseband transceiver with 180 MSPS 13-bit pipelined CMOS ADC and dual 12-bit DACs," IEEE J. Solid-State Circuits, vol.41, no.8, pp. 1856-1866, Aug. 2006.
5. S. M. Louwsma, E. J. M. van Tuijl, M. Vertregt, and B. Nauta, "A 1.35 GS/s, 10b, 175mWtime-interleavedADconverter in 0.13 mCMOS," in VLSI Circuits Symp. Dig., Jun. 2007, pp. 62-63.
6. A. Verma and B. Razavi, "A 10b 500 MHz 55 mW CMOS ADC," in IEEE ISSCC Dig. Tech. Papers, Feb. 2009, pp. 84-85.
7. B. S. Song, M. F. Tompsett, and K. R. Lakshmikumar, "A 12-bit 1-Msample/s capacitor error-averaging pipelined A/D converter," IEEE J. Solid-State Circuits, vol.23, pp. 1324-1333, Dec. 1988.
8. Y.-M. Lin, B. Kim, and P. R. Gray, "A 13-b 2.5-MHz self-calibrated pipelined A/D converter in 3 m CMOS," IEEE J. Solid-State Circuits, vol.26, no.4, pp. 628-636, Apr. 1991.
9. A. N. Karanicolas, H.-S. Lee, and K. L. Barcrania, "A 15-b 1-Msample/s digitally self-calibrated pipeline ADC," IEEE J. Solid-State Circuits, vol.28, no.12, pp. 1207-1215, Dec. 1993.
10. U. Moon and B. S. Song, "Background digital calibration techniques for pipelined ADCs," IEEE Trans. Circuits Syst. II: Analog Digit. Signal Process., vol.44, no.2, pp. 102-109, Feb. 1997.
11. J. Ming and S. H. Lewis, "An 8-bit 80-Msample/s pipelined analog-todigital converter with background calibration," IEEE J. Solid-State Circuits, vol.36, no.10, pp. 1489-1497, Oct. 2001.
12. B. Murmann and B. E. Boser, "A 12-bit 75-MS/s pipelined ADC using open-loop residue amplification," IEEE J. Solid-State Circuits, vol.38, no.12, pp. 2040-2050, Dec. 2003.
13. X. Wang, P. J. Hurst, and S. H. Lewis, "A 12-bit 20-Msample/s pipelined analog-to-digital converter with nested digital background calibration," IEEE J. Solid-State Circuits, vol.39, no.11, pp. 1799-1808, Nov. 2004.
14. E. Siragusa and I. Galton, "A digitally enhanced 1.8-V 15-bit 40-MSample/s CMOS pipelined ADC," IEEE J. Solid-State Circuits, vol.39, no.12, pp. 2126-2138, Dec. 2004.
15. C. R. Grace, P. J. Hurst, and S. H. Lewis, "A 12-bit 80-Msample/s pipelined ADC with bootstrapped digital calibration," IEEE J. Solid- State Circuits, vol.40, no.5, pp. 1038-1046, May 2005.
16. A. Panigada and I. Galton, "A 130 mW 100 MS/s pipelined ADC with 69 dB SNDR enabled by digital harmonic distortion correction," in IEEE ISSCC Dig. Tech. Papers, Feb. 2009, pp. 162-163.
17. T. Cho and P. R. Gray, "A 10 b, 20 Msample/s, 35 mW pipeline A/D converter," IEEE J. Solid-State Circuits, vol.30, no.3, pp. 166-172, Mar. 1995.
18. D.-Y. Chang, "Design techniques for a pipelined ADC without using a front-end sample-and-hold amplifier," IEEE Trans. Circuits Syst. I: Reg. Papers, vol.51, no.11, pp. 2123-2132, Nov. 2004.
19. I. Mehr and L. Singer, "A 55-mW, 10-Bit, 40-Msample/s Nyquist-rate CMOS ADC," IEEE J. Solid-State Circuits, vol.35, no.3, pp. 318-325, Mar. 2000.
20. B. Razavi, Principles of Data Conversion System Design. New York: IEEE Press, 1995.
21. M. Yoshioka, M. Kudo, T. Mori, and S. Tsukamoto, "A 0.8 V 10b 80 MS/s 6.5 mW pipelined ADC with regulated overdrive voltage biasing," in IEEE ISSCC Dig. Tech. Papers, Feb. 2007, pp. 452-453.