A 16b 250MS/s IF-sampling pipelined A/D converter with background calibration

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 53, Issue , 2010, Pages 292-293

  Ali, Ahmed M A ^a   Morgan, Andy ^a   Dillon, Chris ^a   Patterson, Greg ^a   Puckett, Scott ^a   Hensley, Mike ^a   Stop, Russell ^a   Bhoraskar, Paritosh ^a   Bardsley, Scott ^a   Lattimore, David ^a   Bray, Jeff ^a   Speir, Carroll ^a   Sneed, Robert ^a  

^a ANALOG DEVICES INC   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

A/D CONVERTER; AC PERFORMANCE; BI-CMOS PROCESS; CELLULAR COVERAGE; GAIN ERRORS; HIGH RESOLUTION; INPUT BUFFERS; INPUT FREQUENCY; PIPELINED A/D CONVERTERS; SAMPLE RATE; SYSTEM DESIGN; WIRELESS COMMUNICATIONS;

ANALOG TO DIGITAL CONVERSION; JITTER; SIGNAL TO NOISE RATIO; WIRELESS TELECOMMUNICATION SYSTEMS;

CALIBRATION;

EID: 77952206117     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2010.5433923     Document Type: Conference Paper

References (6)

1. A.M.A. Ali, et al., "A 14-bit 125 MS/s IF/RF Sampling Pipelined ADC With 100 dB SFDR and 50 fs Jitter" J. Solid-State Circuits, Vol. 41, no. 8, pp. 1846-1855, Aug. 2006.
2. S. Devirajan, et al., "A 16b 125MS/s 385mW 78.7dB SNR CMOS pipeline ADC", ISSCC Dig. Tech. Papers, pp. 86-87, Feb. 2009.
3. E. Siragusa and I. Galton, "A Digitally Enhanced 1.8-V 15-bit 40-MSample/s CMOS Pipelined ADC," IEEE J. Solid State Circuits, vol. 39, pp. 2126-2138, Dec. 2004.
4. A. Panigada and I. Galton, "A 130mW 100MS/s pipelined ADC with 69dB SNDR enabled by digital harmonic distortion correction", ISSCC Dig. Tech. Papers, pp. 162-163, Feb. 2009.
5. E. Iroaga and B. Murmann, "A 12-Bit 75-MS/s Pipelined ADC Using Incomplete Settling", J. Solid-State Circuits, Vol. 42, no. 4, pp. 748-756, April 2007.
6. B. Murmann and B.E. Boser, "A 12 b 75 MS/s pipelined ADC using open-loop residue amplification", ISSCC Dig. Tech. Papers, pp. 328-497, Vol.1, 2003.