A 10-bit 400-MS/s 160-mW 0.13-μm CMOS dual-channel pipeline ADC without channel mismatch calibration

IEEE Journal of Solid-State Circuits

Volumn 41, Issue 7, 2006, Pages 1596-1605

  Lee, Seung Chul ^a,b   Kim, Kwi Dong ^b   Jong Kee, Kwon ^a,b   Kim, Jongdae ^a,b   Lee, Seung Hoon ^a,c  

^a IEEE   (South Korea)

^b Electronics and Telecommunications Research Institute (ETRI)   (South Korea)

^c Sogang University   (South Korea)

Author keywords

Amplifiers; Analog to digital conversion; Channel mismatch; CMOS analog integrated circuits; Parallel architecture

Indexed keywords

CHANNEL MISMATCH; PARALLEL ARCHITECTURE; SIGNAL-TO-NOISE-AND-DISTORTION RATIO; SINGLE CLOCK-EDGE SAMPLING;

AMPLIFIERS (ELECTRONIC); CALIBRATION; CMOS INTEGRATED CIRCUITS; DC POWER TRANSMISSION; ELECTRIC CLOCKS; ELECTRIC POTENTIAL; ENERGY DISSIPATION; SIGNAL PROCESSING; SOFTWARE PROTOTYPING;

ANALOG TO DIGITAL CONVERSION;

EID: 33746366212     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2006.873862     Document Type: Conference Paper

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