CPU-assisted GPGPU on fused CPU-GPU architectures

Proceedings - International Symposium on High-Performance Computer Architecture

Volumn , Issue , 2012, Pages 103-114

  Yang, Yi ^a   Xiang, Ping ^a   Mantor, Mike ^b   Zhou, Huiyang ^a  

^a North Carolina State University   (United States)

^b ADVANCED MICRO DEVICES   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPILER ALGORITHMS; CPU RESOURCES; FLOATING-POINT COMPUTATION; GPU PROGRAMS; HIGHER FREQUENCIES; INSTRUCTION LEVEL PARALLELISM; L2 CACHES; MEMORY ACCESS; OFF-CHIP MEMORIES; ON CHIPS; PROCESSING UNITS;

AUXILIARY POWER SYSTEMS; BENCHMARKING; COMPUTER ARCHITECTURE; IMAGE CODING; PROGRAM COMPILERS; SUPERCOMPUTERS;

CACHE MEMORY;

EID: 84860322837     PISSN: 15300897     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/HPCA.2012.6168948     Document Type: Conference Paper

References (27)

1. A. Bakhoda, G. Yuan, W. W. L. Fung, H. Wong, and T. M. Aamodt, Analyzing CUDA workloads using a detailed GPU simulator. IEEE International Symposium on Performance Analysis of Systems and Software, April 2009.
2. A. Roth and G. Sohi, Speculative data driven multithreading. IEEE International Symposium on High Performance Computer Architecture, 2001.
3. AMD Accelerated Parallel Processing (APP) SDK V2.3, http://developer.amd. com/gpu/atistreamsdk/pages/default.aspx, 2011
4. C. K. Luk, Tolerating memory latency through software-controlled pre-execution in simultaneous multithreading processors. International Symposium on Computer Architecture, 2001.
5. C. Luk, S. Hong, H. Kim, Qilin: exploiting parallelism on heterogeneous multiprocessors with adaptive mapping. IEEE/ACM International Symposium on Microarchitecture, 2009.
6. C. Zilles and G. Sohi, Execution-based prediction using speculative slices. International Symposium on Computer Architecture, 2001.
7. D. H. Woo, H. S. Lee, COMPASS: a programmable data prefetcher using idle GPU shaders. Proceedings of the Architectural support for programming languages and operating systems, March 13-17, 2010.
8. D. Kim and D. Yeung, Design and evaluation of compiler algorithms for pre-execution. Proceedings of the Architectural support for programming languages and operating systems, 2002.
9. G. Ruetsch and P. Micikevicius, Optimize matrix transpose in CUDA. NVIDIA, 2009.
10. H. Zhou, Dual-Core Execution: Building a Highly Scalable Single-Thread Instruction Window, Proceedings of the International Conference on Parallel Architectures and Compilation Techniques, Sept. 2005
11. J. D. Collins, H. Wang, D. Tullsen, C. Hughes, Y.-F. Lee, D. Lavery, and J. P. Shen, Speculative precomputation: long range prefetching of delinquent loads. International Symposium on Computer Architecture, 2001.
12. J. Lee, N. B. Lakshminarayana, H. Kim, and R. Vuduc, Many-thread aware prefetching mechanisms for gpgpu applications. IEEE/ACM International Symposium on Microarchitecture, 2010.
13. MARSSx86, http://marss86.org/~marss86/index.php/Home
14. N. Govindaraju, B. Lloyd, Y. Dotsenko, B. Smith, and J. Manferdelli, High performance discrete Fourier transforms on graphics processors. Proceedings of Supercomputing, 2008.
15. NVIDIA CUDA C Programming Guide 3.1, 2010.
16. NVIDIA GPU Computing SDK 3.1, http://developer.nvidia.com/gpu-computing- sdk, 2011.
17. O. Mutlu, J. Stark, C. Wilkerson and Y. N. Patt, Run ahead Execution: An Alternative to Very Large Instruction Windows for Out-of-Order Processors. IEEE International Symposium on High Performance Computer Architecture, February 2003.
18. R. Balasubramonian, S. Dwarkadas, and D. Albonesi, Dynamically allocating processor resources between nearby and distant ILP. International Symposium on Computer Architecture, 2001.
19. P. Boudier, Memory System on Fusion APUs - The Benefits of Zero Copy. AMD fusion developer summit, 2011.
20. P. H. Wang, H. Wang, J. D. Collins, E. Grochowski, R. M. Kling, and J. P. Shen, Memory latency-tolerance approaches for Itanium processors: out-of-order execution vs. speculative precomputation. IEEE International Symposium on High Performance Computer Architecture, 2002.
21. Sandy Bridge, http://en.wikipedia.org/wiki/Sandy-Bridge.
22. S. I. Lee, T. Johnson, and R. Eigenmann. Cetus - an extensible compiler infrastructure for source-to-source transformation. In Proc. Workshops on Languages and Compilers for Parallel Computing, 2003
23. S. Ryoo, C. I. Rodrigues, S. S. Stone, S. S. Baghsorkhi, S. Ueng, J. A. Stratton, and W. W. Hwu, Optimization space pruning for a multi-threaded GPU. International Symposium on Code Generation and Optimization, 2008.
24. Y. Solihin, J. Lee and J. Torrellas, Using a user-level memory thread for correlation prefetching, ISCA 2002
25. Streaming SIMD Extensions, http://en.wikipedia.org/wiki/Streaming-SIMD- Extensions.
26. The AMD Fusion Family of APUs, http://sites.amd.com/us/fusion/apu/Pages/ fusion.aspx.
27. Y. Yang, P. Xiang, J. Kong and H. Zhou, A GPGPU Compiler for Memory Optimization and Parallelism Management. ACM SIGPLAN conference on Programming Language Design and Implementation, 2010.