An 8x 10-Gb/s source-synchronous I/O system based on high-density silicon carrier interconnects

IEEE Journal of Solid-State Circuits

Volumn 47, Issue 4, 2012, Pages 884-896

  Dickson, Timothy O ^a   Liu, Yong ^a   Rylov, Sergey V ^a   Dang, Bing ^a   Tsang, Cornelia K ^a   Andry, Paul S ^a   Bulzacchelli, John F ^a   Ainspan, Herschel A ^a   Gu, Xiaoxiong ^a   Turlapati, Lavanya ^a   Beakes, Michael P ^a   Parker, Benjamin D ^a   Knickerbocker, John U ^a   Friedman, Daniel J ^a  

^a IBM T J WATSON RESEARCH CENTER   (United States)

Author keywords

3 D integration; chip to chip communication; DFE IIR; link redundancy; phase rotator; Silicon interposer

Indexed keywords

10 GB/ S; 3-D INTEGRATION; CELL SIZE; CHIP-TO-CHIP COMMUNICATIONS; CHIPSET; DFE-IIR; HIGH-DENSITY; I/O SYSTEMS; INTERCONNECT DENSITIES; PACKAGING TECHNOLOGIES; PB-FREE; PHASE ROTATOR; POWER SUPPLY; RECALIBRATIONS; SILICON CARRIERS; SOI CMOS; SOLDER BUMP; SOURCE SYNCHRONOUS; SYSTEM USE; TIMING RECOVERY SYSTEM; TWO PHASE;

CMOS INTEGRATED CIRCUITS; ENERGY EFFICIENCY; LEAD; REDUNDANCY; VLSI CIRCUITS;

CHIP SCALE PACKAGES;

EID: 84859721885     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2012.2185184     Document Type: Conference Paper

References (12)

1. Top 500 Lists Release, 2011 [Online]. Available: http://www.top500. org/lists
2. J. U. Knickerbocker, C. S. Patel, P. S. Andry, C. K. Tsang, L. P. Buckwalter, E. J. Sprogis, H. Gan, R. R. Horton, R. J. Polastre, S. L.Wright, and J. M. Cotte, "3-D silicon integration and silicon packaging technology using silicon through-vias," IEEE J. Solid-State Circuits, vol. 41, no. 8, pp. 1718-1725, Aug. 2006.
3. B. Dang, D.-Y. Shih, S. Buchwalter, C. Tsang, C. Patel, J. Knickerbocker, P. Gruber, S. Knickerbocker, J. Garant, K. Semkow, K. Ruhmer, and E. Hughlett, "50 m pitch Pb-free micro-bumps by C4NP technology," in Proc. IEEE Electronic Components and Technology Conf., May 2008, pp. 1505-1510.
4. T. O. Dickson, Y. Liu, S. V. Rylov, B.Dang, C.K. Tsang, P. S.Andry, J. F. Bulzacchelli, H. A. Ainspan, X. Gu, L. Turlapati,M. P. Beakes, B. D. Parker, J. U. Knickerbocker, and D. J. Friedman, "An 8 10-Gb/s source-synchronous I/O system based on high-density silicon carrier interconnects," in Symp. VLSI Circuits Dig., Jun. 2011, pp. 80-81.
5. B. Kim, Y. Liu, T. O. Dickson, J. F. Bulzacchelli, and D. J. Friedman, "A 10-Gb/s compact low-power serial I/O with DFE-IIR equalization in 65 nm CMOS," IEEE J. Solid-State Circuits, vol. 44, no. 12, pp. 3526-3538, Dec. 2009.
6. J. F. Bulzacchelli, T. O. Dickson, Z. T. Deniz, H. A. Ainspan, B. D. Parker, M. P. Beakes, S. V. Rylov, and D. J. Friedman, "A78mW11.1 Gb/s 5-tap DFE receiver with digitally calibrated current-integrating summers in 65 nm CMOS," in IEEE Int. Solid-State Circuits Conf. Dig., San Francisco, CA, Feb. 2009, pp. 368-369.
7. D. C. Sessions, "Real-Time Channel Calibration Method and Arrangement," US Patent 6,606,576 B2, Aug. 12, 2003.
8. M. Loh and A. Emami-Neyestanak, "All-digital CDR for high-density, high-speed I/O," in Symp. VLSI Circuits Dig., Jun. 2010, pp. 147-148.
9. J. Poulton, R. Palmer, A. M. Fuller, T. Greer, J. Eyles, W. J. Dally, andM. Horowitz, "A 14-mW6.25-Gb/s transceiver in 90-nm CMOS," IEEE J. Solid-State Circuits, vol. 42, no. 12, pp. 2745-2757, Dec. 2007.
10. T. O. Dickson, J. F. Bulzacchelli, and D. J. Friedman, "A 12-Gb/s, 11-mW half-rate sampled 5-tap decision feedback equalizer with current-integrating summers in 45 nm SOI CMOS technology," IEEE J. Solid-State Circuits, vol. 44, no. 4, pp. 1298-1305, Apr. 2009.
11. F. O'Mahony, J. E. Jaussi, J. Kennedy, G. Balamurugan, M. Mansuri, C. Roberts, S. Shekhar, R. Mooney, and B. Casper, "A 47 10 Gb/s 1.4 mW/Gb/s parallel interface in 45 nm CMOS," IEEE J. Solid-State Circuits, vol. 45, no. 12, pp. 2828-2837, Dec. 2010.
12. X. Gu, L. Turlapati, B. Dang, C. K. Tsang, P. S. Andry, T. O. Dickson, M. P. Beakes, J. U. Knickerbocker, and D. J. Friedman, "High-density silicon carrier transmission line design for chip-to-chip interconnects," in Proc. 20th IEEE Conf. Electrical Performance of Electronic Packaging and Systems, San Jose, CA, Oct. 2011, pp. 37-30.