All-digital CDR for high-density, high-speed I/O

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue , 2010, Pages 147-148

  Loh, Matthew ^a   Emami Neyestanak, Azita ^a  

^a CALIFORNIA INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

All digital; CDR; Static CMOS

Indexed keywords

CMOS INTEGRATED CIRCUITS;

90NM CMOS; ALIGNMENT TECHNIQUE; ALL DIGITAL; CDR; CLOCK PHASE; HIGH SPEED I/O; PHASE ALIGNMENT; PING-PONGS; SOURCE SYNCHRONOUS; STATIC CMOS;

CLOCK AND DATA RECOVERY CIRCUITS (CDR CIRCUITS);

EID: 77957996391     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VLSIC.2010.5560319     Document Type: Conference Paper

References (2)

1. N. Kurd et al, "Next generation Intel® micro-architecture (Nehalem) clocking architecture," IEEE Symposium on VLSI Ciruits, pp.62-63, June 2008
2. J. Tierno et al, "A Wide Power Supply Range, Wide Tuning Range, All Static CMOS All Digital PLL in 65 nm SOI", IEEE J. Solid-State Circuits, vil. 43 pp. 42 - 51, Jan 2008