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Volumn , Issue , 2011, Pages 80-81

An 8x10-Gb/s source-synchronous I/O system based on high-density silicon carrier interconnects

Author keywords

[No Author keywords available]

Indexed keywords

CHANNEL LOSS; HIGH-DENSITY; I/O SYSTEMS; SERIAL I/O; SILICON CARRIERS; SOI CMOS;

EID: 80052675141     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper
Times cited : (14)

References (6)
  • 1
    • 33746875623 scopus 로고    scopus 로고
    • 3-D Silicon Integration and Silicon Packaging Technology Using Silicon Through-Vias
    • Aug.
    • J. Knickerbocker et al., "3-D Silicon Integration and Silicon Packaging Technology Using Silicon Through-Vias," IEEE J. Solid-State Circuits, vol. 41, no. 8, pp. 1718-1725, Aug. 2006.
    • (2006) IEEE J. Solid-State Circuits , vol.41 , Issue.8 , pp. 1718-1725
    • Knickerbocker, J.1
  • 2
    • 70349294332 scopus 로고    scopus 로고
    • A 10-Gb/s Compact, Low-Power Serial I/O with DFE-IIR Equalization in 65nm CMOS
    • Feb.
    • Y. Liu et al., "A 10-Gb/s Compact, Low-Power Serial I/O with DFE-IIR Equalization in 65nm CMOS," ISSCC Dig. Tech. Papers, pp. 182-183, Feb. 2009.
    • (2009) ISSCC Dig. Tech. Papers , pp. 182-183
    • Liu, Y.1
  • 3
    • 29044450805 scopus 로고    scopus 로고
    • A 6.4-Gb/s CMOS SerDes Core with Feed-Forward and Decision-Feedback Equalization
    • Dec.
    • T. Beukema et al., "A 6.4-Gb/s CMOS SerDes Core with Feed-Forward and Decision-Feedback Equalization," IEEE Journal of Solid-State Circuits, vol. 40, no. 12, pp. 2633-2645, Dec. 2005.
    • (2005) IEEE Journal of Solid-State Circuits , vol.40 , Issue.12 , pp. 2633-2645
    • Beukema, T.1
  • 4
    • 80052659236 scopus 로고    scopus 로고
    • Real-time channel calibration method and arrangement
    • U.S. Patent 6606576 B2, Aug. 12
    • D.C. Sessions, "Real-time channel calibration method and arrangement,"U.S. Patent 6606576 B2, Aug. 12, 2003.
    • (2003)
    • Sessions, D.C.1
  • 6
    • 77952157953 scopus 로고    scopus 로고
    • A 47x10Gb/s 1.4mW/(Gb/s) Parallel Interface in 45nm CMOS
    • Feb.
    • F. O'Mahony et al., "A 47x10Gb/s 1.4mW/(Gb/s) Parallel Interface in 45nm CMOS," ISSCC Dig. Tech. Papers, pp. 156-157, Feb. 2010.
    • (2010) ISSCC Dig. Tech. Papers , pp. 156-157
    • O'Mahony, F.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.