A 12-Gb/s 11-mW half-rate sampled 5-tap decision feedback equalizer with current-integrating summers in 45-nm SOI CMOS technology

IEEE Journal of Solid-State Circuits

Volumn 44, Issue 4, 2009, Pages 1298-1305

  Dickson, Timothy O ^a   Bulzacchelli, John F ^a   Friedman, Daniel J ^a  

^a IBM T J WATSON RESEARCH CENTER   (United States)

Author keywords

Current integration; Decision feedback equalizer; Serial link; SOI

Indexed keywords

CMOS INTEGRATED CIRCUITS; INTEGRATION; RAILS;

AREA SAVINGS; CURRENT INTEGRATION; DECISION FEEDBACK EQUALIZER; FEEDBACK ARCHITECTURES; FREQUENCY-DEPENDENT LOSS; HALF RATES; LOW-POWER; RAIL TO RAILS; SERIAL LINK; SERIAL RECEIVERS; SOI; SOI CMOS;

DECISION FEEDBACK EQUALIZERS;

EID: 63449116856     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2009.2014733     Document Type: Conference Paper

References (10)

1. T. Beukema, M. Sorna, K. Seiander, S. Zier, B. L. Ji, P. Murfet, J. Mason, W. Rhee, H. Ainspan, B. Parker, and M. Beakes, "A 6.4-Gb/s CMOS SerDes Core with feed-forward and decision-feedback equalization," IEEE J. Solid-State Circuits, vol. 40, no. 12, pp. 2633-2645, Dec. 2005.
2. R. Payne, P. Landman, B. Bhakta, S. Ramaswamy, S. Wu, J. D. Powers, M. U. Entogan, A.-L. Yee, R. Gu, L. Wu, Y. Xie, B. Parthasarathy, K. Brouse, W. Mohammed, K. Heragu, V. Gupta, L. Dyson, and W. Lee, "A 6.25-Gb/s binary transceiver in 0.13-μm CMOS for serial data transmission across high loss legacy backplane channels," IEEE J. Solid-State Circuits, vol. 40, no. 12, pp. 2646-2657, Dec. 2005.
3. K. Krishna, D. A. Yokoyama-Martin, A. Caffee, C. Jones, M. Loikkanen, J. Parker, R. Segelken, J. L. Sonntag, J. Stonick, S. Titus, D. Weinlader, and S. Wolfer, "A multigigabit backplane transceiver core in 0.13-μm CMOS with a power-efficient equalization architecture," IEEE J. Solid-State Circuits, vol. 40, no. 12, pp. 2658-2666, Dec. 2005.
4. T. O. Dickson, J. F. Bulzacchelli, and D. J. Friedman, "A 12 Gb/s 11 mW half-rate sampled 5-tap decision feedback equalizer with current-integrating summers in 45 nm SOI CMOS technology," in Symp. VLSI Circuits Dig., Jun. 2008, pp. 58-59.
5. S. Sidiropoulos and M. Horowitz, "A 700-Mb/s/pin CMOS signaling interface using current integrating receivers," IEEE J. Solid-State Circuits, vol. 32, no. 5, pp. 681-690, May 1997.
6. K.-L. Wong, A. Rylyakov, and C.-K. K. Yang, "A 5-mW 6-Gb/s quarter-rate sampling receiver with a 2-tap DFE using soft decisions," in Symp. VLSI Circuits Dig., Jun. 2006, pp. 190-191.
7. A. Rylyakov, "An 11 Gb/s 2.4 mW half-rate sampling 2-tap DFE receiver in 65 nm. CMOS," in Symp. VLSI Circuits Dig., Jun. 2007, pp. 272-273.
8. J. F. Bulzacchelli, A. V. Rylyakov, and D. J. Friedman, "Power-efficient decision-feedback equalizers for multi-Gb/s CMOS serial links," in IEEE RFIC Symp., Jun. 2007, pp. 507-510.
9. S.-J. Bae, H.-J. Chi, Y.-S. Sohn, and H.-J. Park, "A 2 Gb/s 2-tap DFE receiver for multi-drop single-ended signaling systems with reduced noise," in IEEE ISSCC Dig. Tech. Papers, Feb. 2004, pp. 244-245.
10. M. Park, J. Bulzacchelli, and D. Friedman, "A 7 Gb/s 9.3 mW 2-tap current-integrating DFE receiver," in IEEE ISSCC Dig. Tech. Papers, Feb. 2007, pp. 230-231.