A 10-Gb/s compact low-power serial I/O with DFE-IIR equalization in 65-nm CMOS

IEEE Journal of Solid-State Circuits

Volumn 44, Issue 12, 2009, Pages 3526-3538

  Kim, Byungsub ^a   Liu, Yong ^b   Dickson, Timothy O ^b   Bulzacchelli, John F ^b   Friedman, Daniel J ^b  

^a USA   (United States)

^b IBM T J WATSON RESEARCH CENTER   (United States)

Author keywords

Backplane channel communication; Chip to chip communication; Compact I O; Continuous time IIR filter; Decision feedback equalizer; Serial link; Silicon carrier links

Indexed keywords

BACKPLANES; CHANNEL COMMUNICATION; CHIP-TO-CHIP COMMUNICATIONS; CONTINUOUS TIME; CONTINUOUS-TIME IIR FILTER; SERIAL LINK; SILICON CARRIERS;

COMMUNICATION; CONTINUOUS TIME SYSTEMS; POWDERS; TRANSMITTERS;

IIR FILTERS;

EID: 72949097916     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2009.2031015     Document Type: Conference Paper

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