High-density silicon carrier transmission line design for chip-to-chip interconnects

2011 IEEE 20th Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS-2011

Volumn , Issue , 2011, Pages 27-30

  Gu, Xiaoxiong ^a   Turlapati, Lavanya ^a   Dang, Bing ^a   Tsang, Cornelia K ^a   Andry, Paul S ^a   Dickson, Timothy O ^a   Beakes, Michael P ^a   Knickerbocker, John U ^a   Friedman, Daniel J ^a  

^a IBM T J WATSON RESEARCH CENTER   (United States)

Author keywords

electrical interconnect; signal integrity; silicon carrier; transmission line

Indexed keywords

CHIP-TO-CHIP COMMUNICATIONS; CHIP-TO-CHIP INTERCONNECTS; DATA RATES; ELECTRICAL INTERCONNECTS; HIGH-DENSITY; LOSS CHARACTERISTICS; LOSS PERFORMANCE; SIGNAL INTEGRITY; SILICON CARRIER; SILICON CARRIERS; STRIP LINE; TEMPERATURE DEPENDENT; TRANSMISSION LINE; TWISTED PAIR;

CHIP SCALE PACKAGES; ELECTRIC LINES; STRIP TELECOMMUNICATION LINES; TRANSMISSION LINE THEORY;

CARRIER COMMUNICATION;

EID: 84855366976     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/EPEPS.2011.6100177     Document Type: Conference Paper

References (10)

1. J. Knickerbocker et al., "3-D Silicon Integration and Silicon Packaging Technology Using Silicon Through-Vias," IEEE J. Solid-State Circuits, vol. 41, no. 8, pp. 1718-1725, Aug. 2006
2. P. Dorsey, "Xilinx Stacked Interconnect Technology White Paper", Oct. 2010. [Online]: http://www.xilinx.com/technology/roadmap/ssi- technology. htm
3. T. Dickson, et al., "An 8x10-Gb/s Source-Synchronous I/O System Based on High-Density Silicon Carrier Interconnects", in Proc. IEEE VLSI Circuits Symposium, June 2011,
4. F. O'Maony et al., "A 47x10Gb/s 1.4mW(Gb/s) Parallel Interface in 45nm CMOS," ISSCC Dig. Tech. Papers, pp. 156-157, Feb. 2010.
5. B. Dang et al., "50μm Pitch Pb-Free Micro-bumps by C4NP Technolgoy," in Proc. IEEE Electronic Components and Technology Conference, pp. 1505-1510, May 2008.
6. CZ2D. [Online]. Available: http://www.alphaworks.ibm.com/tech/eip
7. D. Kam, et al., "Is 25Gb/s On-board Signaling Viable?", IEEE Trans. Adv. Packaging, vol. 32, no. 2, pp. 328-345, May, 2009.
8. Y. Zhang, et al., "On-chip Bus Signaling Using Passive Compensation", in Proc. IEEE Conference on Electrical Performance of Electronic Packaging, pp. 33-36, Oct. 2008.
9. A. Mangan, et al., "De-embedding Transmission Line Measurement for Accurate Modeling of IC Designs", IEEE Trans. Electron Devices, vol. 53, no. 2, pp. 235-241, 2006. (Pubitemid 43174037)
10. Agilent PLTS software 2011 release (v6). [Online]. Available: http://na.tm.agilent.com/plts/help/WebHelp/PLTS.htm