Embedding formal performance analysis into the design cycle of MPSoCs for real-time streaming applications

Transactions on Embedded Computing Systems

Volumn 11, Issue 1, 2012, Pages

  Huang, Kai ^a   Haid, Wolfgang ^a   Bacivarov, Iuliana ^a   Keller, Matthias ^a   Thiele, Lothar ^a  

^a ETH ZURICH   (Switzerland)

Author keywords

Design; Performance

Indexed keywords

ANALYSIS MODELS; DESIGN CYCLE; DESIGN FLOWS; DESIGN SPACE EXPLORATION; DISTRIBUTED OPERATIONS; MULTIPROCESSOR SYSTEMS ON CHIPS; PERFORMANCE; PERFORMANCE ANALYSIS; PROGRAMMING ENVIRONMENT; REAL TIME CONSTRAINTS; REAL TIME STREAMING; REAL-TIME APPLICATION; RUNTIMES; SIMULATION-BASED METHOD; SYSTEM IMPLEMENTATION; SYSTEM VERIFICATIONS;

DESIGN; MICROPROCESSOR CHIPS; SPACE RESEARCH;

MULTIPROCESSING SYSTEMS;

EID: 84859451108     PISSN: 15399087     EISSN: 15583465     Source Type: Journal    
DOI: 10.1145/2146417.2146425     Document Type: Article

References (40)

1. BALSAMO, S.,MARCO, A. D., INVERARDI, P., AND SIMEONI,M. 2004. Model-based performance prediction in software development: A survey. IEEE Trans. Softw. Eng. 30, 5, 295-310.
2. BENINI, L., BERTOZZI, D., ALESSANDRO, B.,MENICHELLI, F., AND OLIVIERI, M. 2005. MPARM: Exploring the multiprocessor soc design space with SystemC. J. VLSI Signal Process. 41, 169-182. (Pubitemid 40997653)
3. BLACK, B. AND SHEN, J. P. 1998. Calibration of microprocessor performance models. Comput. 31, 5, 59-65. (Pubitemid 128556568)
4. CHAKRABORTY, S., KÜNZLI, S., AND THIELE, L. 2003. A general framework for analyzing system properties in platform-based embedded system design. In Proceedings of the Design, Automation and Test in Europe (DATE). 190-195.
5. DENSMORE, D., SANGIOVANNI-VINCENTELLI, A., AND PASSERONE, R. 2006. A platform-based taxonomy for ESL design. IEEE Design Test Comput. 23, 5, 359-374.
6. GERSTLAUER, A., HAUBELT, C., PIMENTEL, A. D., STEFANOV, T., GAJSKI, D. D., AND TEICH, J. 2009. Electronic system-level synthesis methodologies. IEEE Trans. Comput.-Aid. Design Integr. Circuits Syst. 28, 10, 1517-1530.
7. GONZÁLEZHARBOUR,M.,GUTIÉRREZGARCÍA, J. J.,PALENCIAGUTIÉRREZ, J. C., ANDDRAKEMOYANO, J.M. 2001.MAST: Modeling and analysis suite for real time applications. In Proceedings of the Euromicro Conference on Real-Time Systems. 125-134.
8. HAID,W.,KELLER,M.,HUANG, K.,BACIVAROV, I., AND THIELE, L. 2009. Generation and calibration of compositional performance analysis models for multiprocessor systems. In Proceedings of the International Conference on Systems, Architectures, Modeling and Simulation (IC-SAMOS). 92-99.
9. HAID, W. AND THIELE, L. 2007. Complex task activation schemes in system level performance analysis. In Proceedings of the International Conference on HW/SW Codesign and System Synthesis (CODES/ISSS). 173-178. (Pubitemid 351203963)
10. HENIA, R., HAMANN, A., JERSAK, M., RACU, R., RICHTER, K., AND ERNST, R. 2005. System level performance analysis - The SymTA/S approach. IEE Proc.: Comput. Digital Tech. 152, 2, 148-166. (Pubitemid 40718622)
11. JERSAK, M., RICHTER, K., AND ERNST, R. 2005. Performance analysis for complex embedded systems. Int. J. Embedd. Syst. 1, 1-2, 33-49.
12. JONSSON, B.,PERATHONER, S.,THIELE, L., AND YI,W. 2008. Cyclic dependencies in modular performance analysis. In Proceedings of the International Conference on Embedded Software (EMSOFT). 179-188.
13. KAHLE, J., DAY, M., HOFSTEE, H., JOHNS, C., MAEURER, T., AND SHIPPY, D. 2005. Introduction to the cell multiprocessor. IBM J. Res. Develop. 49, 4/5, 589-604. (Pubitemid 41398407)
14. KAHN, G. 1974. The semantics of a simple language for parallel programming. In Proceedings of the IFIP Congress. 471-475.
15. KANGAS, T., KUKKALA, P., ORSILA, H., SALMINEN, E., HÄNNIKÄINEN, M., AND HÄMÄLÄINEN, T. D. 2006. UML-based multiprocessor soc design framework. ACM Trans. Embedd. Comput. Syst. 5, 2, 281-320.
16. KÜNZLI, S., POLETTI, F.,BENINI, L., AND THIELE, L. 2006. Combining simulation and formal methods for systemlevel performance analysis. In Proceedings of the Design, Automation and Test in Europe (DATE). 236-241.
17. LAHIRI, K., RAGHUNATHAN, A., AND DEY, S. 2001. System-level performance analysis for designing on-chip communication architectures. IEEE Trans. Comput.-Aid. Design Integr. Circuits Syst. 20, 6, 768-783. (Pubitemid 32576327)
18. LAMPKA, K., PERATHONER, S., AND THIELE, L. 2010. Analytic real-time analysis and timed automata: A hybrid methodology for the performance analysis of embedded real-time systems. Des. Autom. Embedd. Syst. 14, 3, 193-227.
19. LE BOUDEC, J.-Y. AND THIRAN, P. 2001. Network Calculus -A Theory of Deterministic Queuing Systems for the Internet. Lecture Notes in Computer Science, vol. 2050. Springer-Verlag, Berlin, Germany.
20. LEE, E. A. AND MESSERSCHMITT, D. G. 1987. Synchronous data flow. Proc. IEEE 75, 9, 1235-1245.
21. LEE, E. A. AND PARKS, T. M. 1995. Dataflow Process Networks. Proc. IEEE 83, 5, 773-799.
22. MAXIAGUINE, A., KÜNZLI, S., AND THIELE, L. 2004. Workload characterization model for tasks with variable execution demand. In Proceedings of the Design, Automation and Test in Europe (DATE). 1040-1045.
23. PAOLUCCI, P., JERRAYA, A., LEUPERS, R., THIELE, L., AND VICINI, P. 2006. SHAPES: A tiled scalable software hardware architecture platform for embedded systems. In Proceedings of the International Conference HW/SW Codesign and System Synthesis (CODES/ISSS). 167-172. (Pubitemid 47113032)
24. PELLIZZONI, R. AND CACCAMO, M. 2007. Toward the predictable integration of real-time COTS-based systems. In Proceedings of the Real-Time Systems Symposium (RTSS). 73-82.
25. PERATHONER, S., REIN, T., THIELE, L., LAMPKA, K., AND ROX, J. 2010. Modeling structured event streams in system level performance analysis. In Proceedings of the ACM Conference on Languages, Compilers and Tools for Embedded Systems (LCTES).
26. PERATHONER, S., WANDELER, E., THIELE, L., HAMANN, A., SCHLIECKER, S., HENIA, R., RACU, R., ERNST, R., AND GONZÁLEZ HARBOUR, M. 2009. Influence of different abstractions on the performance analysis of distributed hard real-time systems. Des. Autom. Embedd. Syst. 13, 1, 27-49.
27. PETRIU, D., SHOUSHA, C., AND JALNAPURKAR, A. 2000. Architecture-based performance analysis applied to a telecommunication system. IEEE Trans. Softw. Eng. 26, 11, 1049-1065. (Pubitemid 32076244)
28. PIMENTEL, A., ERBAS, C., AND POLSTRA, S. 2006. A systematic approach to exploring embedded system architectures at multiple abstraction levels. IEEE Trans. Comput. 55, 2, 99-112.
29. PIMENTEL, A. D., THOMPSON, M., POLSTRA, S., AND ERBAS, C. 2008. Calibration of abstract performance models for system system-level design space exploration. J. Signal Process. Syst. 50, 2, 99-114.
30. RTEMS STEERING COMMITTEE. 2010. RTEMS. http://www.rtems.com.
31. THIELE, L.,BACIVAROV, I.,HAID,W., ANDHUANG,K. 2007. Mapping-applications to tiledmultiprocessor embedded systems. In Proceedings of the International Conference on Application of Concurrency to System Design (ACSD). 29-40.
32. THIELE, L. AND STOIMENOV, N. 2009. Modular performance analysis of cyclic dataflow graphs. In Proceedings of the International Conference on Embedded Software (EMSOFT). 127-136.
33. THIES, W., KARCZMAREK, M., AND AMARASINGHE, S. 2002. StreamIt: A language for streaming applications. In Proceedings of the 11th International Conference on Compiler Construction. 179-196.
34. VIEHL, A., SCHÖNWALD, T., BRINGMANN, O., AND ROSENSTIEHL, W. 2006. Formal performance analysis and simulation of UML/SysML models for ESL design. In Proceedings of the Design, Automation and Test in Europe (DATE). 242-247.
35. WANDELER, E. AND THIELE, L. 2006a. Interface-based design of real-time systems with hierarchical scheduling. In Proceedings of the Real-Time and Embedded Technology and Applications Symposium (RTAS). 243-252. (Pubitemid 44539775)
36. WANDELER, E. AND THIELE, L. 2006b. Optimal TDMA time slot and cycle length allocation for hard real-time systems. In Proceedings of the Asia and South Pacific Conference on Design Automation (ASP-DAC). 479-484. (Pubitemid 44375976)
37. WANDELER, E. AND THIELE, L. 2006c. Real-Time Calculus (RTC) toolbox. http://www.mpa.ethz.ch/Rtctoolbox.
38. WANDELER, E., THIELE, L., VERHOEF, M., AND LIEVERSE, P. 2006. System architecture evaluation using modular performance analysis: A case study. Int. J. Softw. Tools Technol. Transfer 8, 6, 649-667. (Pubitemid 44650616)
39. WILHELM, R., ENGBLOM, J., ERMEDAHL, A., HOLSTI, N., THESING, S., WHALLEY, D., BERNAT, G., FERDINAND, C., HECKMANN, R., MITRA, T., MUELLER, F., PUAUT, I., PUSCHNER, P., STASCHULAT, J., AND STENSTRÖM, P. 2008. The worst-case execution time problem - Overview of methods and survey of tools. ACM Trans. Embedd. Comput. Syst. 7, 3, 36:1-36:53.
40. WOODSIDE, M. 2007. From annotated software designs (UML SPT/MARTE) to model formalisms. Lecture Notes in Computer Science, vol. 4486. Springer-Verlag, Berlin, Germany, 429-467.