Performance analysis for complex embedded applications

International Journal of Embedded Systems

Volumn 1, Issue 1-2, 2005, Pages 33-49

  Jersak, Marek ^a   Richter, Kai ^a   Ernst, Rolf ^b  

^a Symtavision GmbH

^b TECHNICAL UNIVERSITY OF BRAUNSCHWEIG   (Germany)

Author keywords

complex applications; performance analysis; reactive multiprocessor systems

Indexed keywords

EID: 47849090321     PISSN: 17411068     EISSN: 17411076     Source Type: Journal    
DOI: 10.1504/ijes.2005.008807     Document Type: Article

References (37)

1. Buttazzo, G. (2002) Real-Time Computing Systems – Predictable Scheduling Algorithms and Applications, Kluwer Academic Publishers, ISBN 0-7923-9994-3.
2. Chakraborty, S., Kunzli, S. and Thiele, L. (2003) ‘A general framework for analysing system properties in platform-based embedded system designs’, Proc. DATE‘03, Munich, Germany, March, pp.190–195.
3. Cruz, R.L. (1991) ‘A calculus for network delay’, IEEE Transactions on Information Theory, Vol. 37, No. 1, January, pp.114–141.
4. Eles, P., Kuchcinski, K., Peng, Z., Pop, P. and Doboli, A. (1998) ‘Scheduling of conditional process graphs for the synthesis of embedded systems’, Proc. Design, Automation and Test in Europe – DATE, Paris, France, pp.132–138.
5. Fidge, C.J. (1998) ‘Real-time schedulability tests for preemptive multitasking’, Real-Time Systems, Vol. 14, pp.61–93.
6. Gresser, K. (1993) Echtzeitnachweis Ereignisgesteuerter Realzeitsysteme, PhD Dissertation, Technische Universitat Miinchen.
7. Jersak, M. (2004) Performance Analysis for Complex Embedded Applications, PhD Dissertation, Technical University of Braunschweig, http://opus.tu-bs.de/opus/volltexte/2005/707/pdf/Marek_Jersak_Dissertation.pdf
8. Jersak, M. and Ernst, R. (2003) ‘Enabling scheduling analysis of heterogeneous systems with multi-rate data dependencies and rate intervals’, Proceeding 40th Design Automation Conference, Annaheim, USA, June, pp.454–459.
9. Jersak, M., Henia, R. and Ernst, R. (2004) ‘Context-aware performance analysis for efficient embedded system design’, Proc. of Design, Automation and Test in Europe Conference (DATE ‘04), Paris, France, February, pp.1046–1051.
10. Kopetz, H. and Gruensteidl, G. (1993) ‘TTP – a time-triggered protocol for fault-tolerant computing’, Proceedings 23rd International Symposium on Fault-Tolerant Computing, pp.524–533.
11. Lee, E.A. and Messerschmitt, D. (1987b) Static Scheduling of Synchronous Data Flow Programs for Digital Signal Processing, Vol. 36, No. 1, January, pp.42–35.
12. Lee, E.A. and Messerschmitt, D.G. (1987a) ‘Synchronous dataflow’, Proceedings of the IEEE, Vol. 75, No. 9, pp.1235–1245.
13. Lee, E.A. and Sangiovanni-Vincentelli, A. (1998) ‘A framework for comparing models of computation’, IEEE Trans. CAD, December.
14. Liu, C.L. and Layland, J.W. (1973) ‘Scheduling algorithm for multiprogramming in a hard-real-time environment’, Journal of the ACM, Vol. 20, pp.46–61.
15. Parekh, A.K. and Gallager, R.G. (1993) ‘A generalized processor sharing approach to flow control in integrated services networks: the single-node case’, IEEE/ACM Transactions on Networking, Vol. 1, No. 3, June, pp.344–257.
16. Pop, T., Eles, P. and Peng, Z. (2002) ‘Holistic scheduling and analysis of mixed time/event-triggered distributed embedded systems’, Tenth International Symposium on Hardware/Software Codesign (CODE’02), Estes Park, Colorado, USA, May, pp.187–192.
17. Richter, K., Jersak, M. and Ernst, R. (2003a) ‘A formal approach to MpSoC performance verification’, IEEE Computer, Vol. 36, No. 4, April, pp.60–67.
18. Richter, K., Racu, R. and Ernst, R. (2003b) ‘Scheduling analysis integration for heterogeneous multiprocessor SoC’, Proceedings 24th International Real-Time Systems Symposium (RTSS’03), Cancun, Mexico, December, pp.236–245.
19. Sgroi, M., Lavagno, L. and Sangiovanni-Vincentelli, A. (2000) ‘Formal models for embedded system design’, IEEE Design and Test of Computers, Vol. 17, No. 2, pp.14–27.
20. Thiele, L., Chakraborty, S., Gries, M. and Kunzli, S. (2002) ‘Design space exploration of network processor architectures’, in Franklin, M., Crowley, P., Hadimioglu, H. and Onufryk, P. (Eds.): Network Processor Design Issues and Practices, Vol. 1, Morgan Kaufmann, October, Chapter 4, pp.55–90.
21. Tindell, K.W. (1994) ‘An extendible approach for analysing fixed priority hard real-time systems’, Journal of Real-Time Systems, Vol. 6, No. 2, March, pp.133–152.
22. Xie, Y. and Wolf, W. (2001) ‘Allocation and scheduling of conditional task graph in hardware/software co-synthesis’, Proc. Design, Automation and Test in Europe (DATE’01), Munich, Germany, March, pp.620–625.
23. Yen, T. and Wolf, W. (1998) ‘Performance estimation for real-time distributed embedded systems’, IEEE Transactions on Parallel and Distributed Systems, Vol. 9, No. 11, November, pp.1125–1136.
24. Ziegenbein, D. (2003) A Compositional Approach to Embedded System Design, PhD Dissertation, Technical University of Braunschweig, Germany, http://opus.tu-bs.de/opus/volltexte/2003/405/pdf/Dissertation.pdf
25. Ziegenbein, D., Richter, K., Ernst, R., Thiele, L. and Teich, J. (2002) ‘SPI – a system model for heterogeneously specified embedded systems’, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 10, No. 4, August, pp.379–389.
26. This of course implies that the feed-forward system is not overloaded and can be analysed.
27. Remember that C requires at least three tokens for one activation. Therefore, no two simultaneous activations can be observed when four tokens are available, even though it is possible that only four tokens are consumed in two subsequent consumer executions.
28. AutoBox, dSPACE, http://www.dspace.de/ww/en/pub/products/prodover/modularhardwareintroduction/accessories/autobox.htm.
29. LabCar, ETAS, http://en.etasgroup.com/vcycle/testingval/index.shtml.
30. MaxSim Development Suite, AXYS Design, http://www.axysdesign.com/products/productsmaxsim.asp.
31. RAPID RMA, Tri-Pacific Software, Inc., http://www.tripac.com/html/prod-fact-rrm.html.
32. Realogy Real-Time Architect Overview, LiveDevices Inc, http://www.livedevices.com/realtime.shtml.
33. Seamless Co-Verification Environment, Mentor Graphics, http://www.mentorg.com/seamless/.
34. Semiconductor Industry Association (2001) International Technology Roadmap for Semiconductors, http://public.itrs.net/Files/2001ITRS/Home.htm.
35. SiliconBackplane μNetwork, Sonics, http://www.sonicsinc.com/Pages/Networks.html.
36. SymTA/S – symbolic timing analysis for systems, http://www.ida.ing.tu-bs.de/research/projects/symta-s/.
37. TimeSys, TimeSys, http://www.timesys.com/.