SCOPUS 정보 검색 플랫폼

Microelectronics Reliability

Volumn 52, Issue 4, 2012, Pages 688-691

Resistive switching behavior of a CeO 2 based ReRAM cell incorporated with Si buffer layer

(9) Dou, C a Kakushima, K a Ahmet, P a Tsutsui, K a Nishiyama, A a Sugii, N a Natori, K a Hattori, T a Iwai, H a

a TOKYO INSTITUTE OF TECHNOLOGY (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CONDUCTIVE FILAMENTS; DEVICE PERFORMANCE; MEMORY PERFORMANCE; OPERATION POWER; OPERATION VOLTAGE; RESISTIVE SWITCHING; RESISTIVE SWITCHING BEHAVIORS; SI LAYER;

BUFFER LAYERS; SILICATES; SWITCHING SYSTEMS;

SILICON;

EID: 84857788713 PISSN: 00262714 EISSN: None Source Type: Journal
DOI: 10.1016/j.microrel.2011.10.019 Document Type: Article

Times cited : (40)

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