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Volumn 98, Issue 7, 2011, Pages

Grain boundary assisted degradation and breakdown study in cerium oxide gate dielectric using scanning tunneling microscopy

(9) Shubhakar, K a Pey, K L a Kushvaha, S S b O'Shea, S J b Raghavan, N a Bosman, M b Kouda, M c Kakushima, K c Iwai, H c

a NANYANG TECHNOLOGICAL UNIVERSITY (Singapore)

b INSTITUTE OF MATERIALS RESEARCH AND ENGINEERING (Singapore)

c TOKYO INSTITUTE OF TECHNOLOGY (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CERIUM OXIDES; DEGRADATION RATE; DIELECTRIC DEGRADATION; ELECTRICAL CONDUCTION; ELECTRICAL PERFORMANCE; ELECTRICAL STUDIES; GATE STACKS; METAL OXIDE SEMICONDUCTOR; NANO SCALE; POLYCRYSTALLINE; STRESS-INDUCED; TIME-DEPENDENT DIELECTRIC BREAKDOWN;

CERIUM; CERIUM COMPOUNDS; DEGRADATION; ELECTRIC PROPERTIES; GATE DIELECTRICS; GATES (TRANSISTOR); GRAIN BOUNDARIES; GRAIN SIZE AND SHAPE; LEAKAGE CURRENTS; OXIDES; POLYCRYSTALLINE MATERIALS; SCANNING TUNNELING MICROSCOPY; SEMICONDUCTOR INSULATOR BOUNDARIES; SEMICONDUCTOR METAL BOUNDARIES; SOLVENTS;

DIELECTRIC MATERIALS;

EID: 79951922662 PISSN: 00036951 EISSN: None Source Type: Journal
DOI: 10.1063/1.3553190 Document Type: Article

Times cited : (30)

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